On the minimum computation time of functions

Cook, Stephen A.; Aanderaa, Stål

doi:10.1090/s0002-9947-1969-0249212-8

Cited by 156 publications

(43 citation statements)

References 9 publications

(2 reference statements)

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“…Knuth proposes a modified version in [10]. Toom and Cook (TC) propose in [11], [12] algorithms for decomposition with 3 and more parts with O(n 1.47 ) complexity. Fast Fourier Transform (FFT) reduces complexity to O(n log n log log n) using Schönhage and Strassen algorithm [13].…”

Section: B Multiplication Algorithmsmentioning

confidence: 99%

Towards FHE in Embedded Systems: A Preliminary Codesign Space Exploration of a HW/SW Very Large Multiplier

Abozaid

Tisserand

El-Mahdy

et al. 2015

IEEE Embedded Syst. Lett.

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The integration of fully homomorphic encryption (FHE) into embedded systems is limited due to its huge computational requirements. FHE requires multiplications of operands up to millions of bits. Current implementations use high-end and parallel processors, leading to high-power consumption. We propose a hardware-software system to benefit from the best of hardware (performance/low-power) and software (flexibility) capabilities. In this letter we present our first co-design results for hardware dedicated multiplication units, which is used as atomic operations by the software layer. We report FPGA implementation results for those units and software performance estimations of their use in multiplications up to 16 millions-bit operands. In range of 10 W power consumption, our analysis show that good FHE performance is affordable.

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Section: B Multiplication Algorithmsmentioning

confidence: 99%

Towards FHE in Embedded Systems: A Preliminary Codesign Space Exploration of a HW/SW Very Large Multiplier

Abozaid

Tisserand

El-Mahdy

et al. 2015

IEEE Embedded Syst. Lett.

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“…[1][2][3][4] Starting from the matrix defined by˘∞, 2, 1, −1, 1 2 , − 1 2 , 0} we obtained the below IS, with weight A. [3][4][5] Starting from the matrix defined by˘∞, −2, 1 2 , 4, 2, −1, 1, − 1 2 , 0¯we obtained the below IS, with weight 32 · STEP + 5 · DIV + 2 · SHIFT + 6 ·( 1 X) + 8 · ( 1 2 …”

Section: A Toom-4 Toom-45 and Toom-5mentioning

confidence: 99%

“…Starting with the works of Karatsuba [9], Toom [12] and Cook [5], who found methods to lower asymptotic complexity for polynomial multiplication from O(n 2 ) to O(n 1+ ) with 0 < < 1, many efforts have been done in finding optimised implementations in arithmetic software [6,8,10].…”

Section: Introductionmentioning

confidence: 99%

Integer and polynomial multiplication

Bodrato

Zanoni

2007

Proceedings of the 2007 International Symposium on Symbolic and Algebraic Computation

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Karatsuba and Toom-Cook are well-known methods used to multiply efficiently long integers. There have been different proposal about the interpolating values used to determine the matrix to be inverted and the sequence of operations to invert it. A definitive word about which is the optimal matrix (values) and the (number of) basic operations to invert it seems still not to have been said. In this paper we present some particular examples of useful matrices and a method to generate automatically, by means of optimised exhaustive searches on a graph, the best sequence of basic operations to invert them.

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“…Whether or not it is possible to multiply two numbers in purely linear time is still an open problem, assuming purely sequential implementation. Under some restrictive assumptions it is possible to prove [8] a lower bound of Ω(k log k) elementary bit operations.…”

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confidence: 99%

A low-voltage, micro-power 1 A switching regulator

Pietkiewicz¹

1990

1990 37th IEEE International Conference on Solid-State Circuits

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In this paper we shall introduce several new algorithms for integer multiplication that are based on specific multiple-radix representation of one of the multiplicands. We provide extensive theoretical analysis and experimental results for multipliers based on the new representations on 0.18 μm CMOS technology. They provide a clear picture about the advantages of the new method in 64-bit hardware implementations compared to array based classical multiplier and radix-8 based multiplier. The proposed multipliers have better area and power consumption compared to reference multipliers.

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On the minimum computation time of functions

Cited by 156 publications

References 9 publications

Towards FHE in Embedded Systems: A Preliminary Codesign Space Exploration of a HW/SW Very Large Multiplier

Towards FHE in Embedded Systems: A Preliminary Codesign Space Exploration of a HW/SW Very Large Multiplier

Integer and polynomial multiplication

A low-voltage, micro-power 1 A switching regulator

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