Towards FHE in Embedded Systems: A Preliminary Codesign Space Exploration of a HW/SW Very Large Multiplier

Abstract

The integration of fully homomorphic encryption (FHE) into embedded systems is limited due to its huge computational requirements. FHE requires multiplications of operands up to millions of bits. Current implementations use high-end and parallel processors, leading to high-power consumption. We propose a hardware-software system to benefit from the best of hardware (performance/low-power) and software (flexibility) capabilities. In this letter we present our first co-design results for hardware dedicated multiplication units, which is used as atomic operations by the software layer. We report FPGA implementation results for those units and software performance estimations of their use in multiplications up to 16 millions-bit operands. In range of 10 W power consumption, our analysis show that good FHE performance is affordable.

Design Space Exploration for a Co-designed Accelerator Supporting Homomorphic Encryption

“…SOFTWARE/HARDWARE CO-DESIGNED ACCELERATOR A software/hardware co-designed accelerator supporting FHE is proposed in [4]. It is basically constructed from two parts: dedicated hardware on FPGA and software running on processor core(s), see Figure 1.…”

“…The SPM is utilises pipelined computations and local communications to improve the operating frequency [22]. We used the SPM rectangular multiplier proposed in [3], [4] which is an optimised word-level version. The architecture of the adopted modified SPM is presented in Figure 2: The parallel operand, A (w-bit), is partitioned into k-bit sub-words.…”

“…Using our analytical model and the Zynq XC7Z045-3 FPGA, we estimated the computation time for wide range of operand widths (n ∈ [1, 32] Mbits) and single SPM or [4] are used. Also for SB based multiplier, the number of DSP and BRAM blocks in the FPGA are used to estimate the number of SB units that would fit in the FPGA.…”

“…In this paper we explore the design space of SW/HW codesigned multiplier [4] that integrates a large operand width multiplier with correspondingly fast software multiplication algorithms. The rationale here is that while fast software implementations are asymptotically fast, their practical implementation is usually not as fast, generally due to relatively large operations overheads.…”