On the Minimization of the Width of the Control Memory of Microprogrammed Processors

Baer,; Koyama,

doi:10.1109/tc.1979.1675352

Cited by 29 publications

(4 citation statements)

References 6 publications

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“…The encoding of collections of outputs (COs) is an SD-based method having its roots in the microprogram control units [44]. In the 1950s, this method was used for reducing the number of bits in control memory words [45]. Next, it was used to optimize hardware of FSM circuits implemented with various programmable logic devices [2].…”

Section: Optimizing Circuits Of Fpga-based Mealy Fsmsmentioning

confidence: 99%

Improving Characteristics of FSMs With Mixed Codes of Outputs

et al. 2022

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Practically, any digital system includes sequential blocks. This paper considers a case when LUT-based sequential blocks are represented by Mealy finite state machines (FSMs). The LUT count is one of the most important characteristics of an FSM circuit. In this paper, a method is proposed which aims at decreasing the LUT counts of FPGA-based Mealy FSMs with mixed encoding of the collections of outputs. To do it, a method of encoding of the fields of compatible states is proposed. The proposed approach leads to LUT-based Mealy FSM circuits having three levels of logic blocks. Each function for any logic level is represented by a circuit including a single LUT. There is given an example of FSM synthesis with the proposed method. The experiments are conducted using standard benchmark FSMs. The results of experiments show that the proposed approach produces LUT-based circuits with fewer LUTs than it is for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, the mixed encoding the collections of outputs). The LUT count is decreased by an average of 6.97 to 62.85 percent. These improvements are accompanied by a slight decrease in the maximum operating frequency. The frequency is decreased by up to 8.09%. The advantages of the proposed method increase as the number of FSM inputs and states increases. INDEX TERMSMealy FSM, FPGA, LUT, synthesis, mixed encoding of collections of outputs, fields of compatible states.

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Section: Optimizing Circuits Of Fpga-based Mealy Fsmsmentioning

confidence: 99%

Improving Characteristics of FSMs With Mixed Codes of Outputs

et al. 2022

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“…For example, MPY FSMs could be implemented using MXs, PLAs, and PROMs (Figure 15). Different approaches were used for optimizing characteristics of PLA-based FSMs [76][77][78][79][80][81][82]. One of the new approaches was an encoding of FSM terms [78], leading to PH FSMs.…”

Section: Structural Decomposition In Spld-based Fsmsmentioning

confidence: 99%

Structural Decomposition in FSM Design: Roots, Evolution, Current State—A Review

2021

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The review is devoted to methods of structural decomposition that are used for optimizing characteristics of circuits of finite state machines (FSMs). These methods are connected with the increasing the number of logic levels in resulting FSM circuits. They can be viewed as an alternative to methods of functional decompositions. The roots of these methods are analysed. It is shown that the first methods of structural decomposition have appeared in 1950s together with microprogram control units. The basic methods of structural decomposition are analysed. They are such methods as the replacement of FSM inputs, encoding collections of FSM outputs, and encoding of terms. It is shown that these methods can be used for any element basis. Additionally, the joint application of different methods is shown. The analysis of change in these methods related to the evolution of the logic elements is performed. The application of these methods for optimizing FPGA- based FSMs is shown. Such new methods as twofold state assignment and mixed encoding of outputs are analysed. Some methods are illustrated with examples of FSM synthesis. Additionally, some experimental results are represented. These results prove that the methods of structural decomposition really improve the characteristics of FSM circuits.

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“…The problem of reducing the size of the ROM microprogram that emulates an instruction set architecture on a given hardware organization has received considerable attention from two directions. The first ap proach [3]- [5] tries to reduce the number of words in the control memory specification by identifying inherent and unused parallelism in a given microprogram and by combining those microoperations that can be issued simultaneously into fewer words to be issued in sequence; this then attempts to reduce the word dimension of the ROM. The second approach tries to identify and group microop erations that cannot be issued simultaneously, so that they can be encoded together in a field to reduce the width of the control memory word.…”

Section: Introductionmentioning

confidence: 99%

Comments on “algorithms for reporting and counting geometric intersections”

Brown

1981

IEEE Trans. Comput.

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It is noticed that the original disjoint subsets of each set appear in different groups. Hence, the three sets are steerable.Q.E.D. Based on the above lemmas we state the following theorem.Theorem 2: The sets of microcommands C, (i = 1, 2, · · ·, n) are steerable together if and only if the following conditions are satis fied:1) The sets are pairwise steerable.2) The disjoint subsets with distinct steering code of each set Q are the same when the set C, is steered with each of the remaining (« -1) sets.An example of three set steerability is shown in Fig. 7 for the sample microprogram. The disjoint groups are \(d Nop)(e Nop)(A)l and |(#)(i)(Nop)j. III. CONCLUSIONSWhen we obtain the minimum bit solution based on the formulation of Grasselli and Montanari [2], it may not turn out to be a good en gineering reduction as was pointed out by Agerwala [6]. We may then employ the technique of bit steering for further reduction in the bit dimension and obtain a good engineering solution. The concurrency matrix method presented in this paper is very useful in the detection of bit steerability and the encoding of two (or more) mutually ex clusive sets of microcommands. IV.Abstract-Bentley and Ottmann 1 present an algorithm for reporting all Κ intersections among Ν planar line segments in 0((7V + K) log N) time and 0(7V + A") storage. With a small modification that storage requirement can be re duced to 0(N) with no increase in computation time, which is important because Κ can grow as Θ(Ν 2 ).Index Terms-Computational geometry, geometric intersection problems, optimal algorithms, VLSI design rule checking.

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On the Minimization of the Width of the Control Memory of Microprogrammed Processors

Cited by 29 publications

References 6 publications

Improving Characteristics of FSMs With Mixed Codes of Outputs

Improving Characteristics of FSMs With Mixed Codes of Outputs

Structural Decomposition in FSM Design: Roots, Evolution, Current State—A Review

Comments on “algorithms for reporting and counting geometric intersections”

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