Structural Decomposition in FSM Design: Roots, Evolution, Current State—A Review

Barkalov, Alexander; Titarenko, Larysa; Krzywicki, Kazimierz

doi:10.3390/electronics10101174

Cited by 15 publications

(104 citation statements)

References 95 publications

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“…In this case, a resulting circuit is multi-level. As a rule, it has a complicated system of "spaghetti-type" interconnections [21].…”

Section: Luterfmentioning

confidence: 99%

“…is violated, then there are several levels of LUTs in an FSM circuit. Various methods have been developed for improving characteristics of FSM circuits [21,25,26,30,34,[41][42][43][44].…”

Section: Related Workmentioning

confidence: 99%

“…However, the circuit characteristics depend strongly on the number of FSM inputs. This is due to the limited number of LUT inputs [21]. For example, the experiments [58] definitely show the following: if there is L > 10, then using maximum binary codes leads to FSM circuits with better characteristics than the circuits based on one-hot codes.…”

Section: Related Workmentioning

confidence: 99%

“…The methods of FD are used by both academic and industrial CAD tools dealing with FPGA-based design. Unfortunately, this approach has a serious drawback: FD-based FSM circuits have complicated systems of "spaghetti-type" interconnections [21]. This drawback is manifested in the increasing for both cycle time and power consumption of a resulting FSM circuit [59].…”

Section: Related Workmentioning

confidence: 99%

“…To optimize the basic characteristics of FSM circuits, the methods of structural decomposition (SD) can be used [21]. These methods allow structuring an LUT-based FSM circuit and presenting it as a composition of several large logical blocks.…”

Section: Introductionmentioning

confidence: 99%

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Using Codes of Output Collections for Hardware Reduction in Circuits of LUT-Based Finite State Machines

et al. 2022

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A method is proposed which aims to reduce the hardware in FPGA-based circuits of Mealy finite state machines (FSMs). The proposed method is a type of structural decomposition method. Its main goal is the reducing the number of look-up table (LUT) elements in FSM circuits compared to the three-block FSM circuit. The main idea of the proposed method is the using codes of collections of FSM outputs for replacing the FSM inputs and state variables. The interstate transitions are defined using collections of outputs generated in two adjacent cycles of synchronization. One, of output collection codes, is kept into a register. To optimize block-generating FSM outputs, a new type of state codes is proposed. A state is encoded as an element of some class of states. This approach allows both the number of logic levels and inter-level interconnections in LUT-based FSM circuit to be diminished. An example of an LUT-based Mealy FSM circuit with the proposed method applied is shown. Moreover, the results of our research are represented. The research was conducted using the CAD tool Vivado by Xilinx. The experiments prove that the proposed approach allows the reduction of hardware compared with such known methods as Auto and One-hot of Vivado, and JEDI. Moreover, the proposed approach gives better results than a method based on the simultaneous replacement of inputs and encoding collections of outputs. Compared to circuits of the three-block FSMs, the LUT counts are reduced by an average of 10.07% without significant reduction in the value of operating frequency. The gain in LUT counts increases with the increasing the numbers of FSM states and inputs.

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“…In this case, a resulting circuit is multi-level. As a rule, it has a complicated system of "spaghetti-type" interconnections [21].…”

Section: Luterfmentioning

confidence: 99%

“…is violated, then there are several levels of LUTs in an FSM circuit. Various methods have been developed for improving characteristics of FSM circuits [21,25,26,30,34,[41][42][43][44].…”

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Using Codes of Output Collections for Hardware Reduction in Circuits of LUT-Based Finite State Machines

et al. 2022

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Optimization based on the minimum maximal k-partial-matching problem of finite states machines with input multiplexing

García-Vargas

Senhadji-Navarro

2022

Des Autom Embed Syst

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Finite State Machines with Input Multiplexing (FSMIMs) were proposed in previous work as a technique for efficient mapping Finite State Machines (FSMs) into ROM memory. In this paper, we present new contributions to the optimization process involved in the implementation of FSMIMs in Field Programmable Gate Array (FPGA) devices. This process consists of two stages: (1) the simplification of the bank of input selectors of the FSMIM, and (2) the reduction of the depth of the ROM. This has a significant impact both on the number of used Look-Up Tables (LUTs) and on the number of the Embedded Memory Blocks (EMBs) required by the ROM. For the first stage, we present two approaches to optimize FSMIM implementations based on the Minimum Maximal k-Partial Matching (MMKPM) problem: one of them applies the greedy algorithm for the MMKPM problem, and the other based on a new multiobjetive variant of the MMKPM and its corresponding Integer Linear Programing formulation. We also propose a modification of the second stage, in which the characteristics of EMBs are taken into account to improve implementation results. The new optimization process significantly reduces the number of used FPGA resources with respect to the previous one. In addition, the proposed approaches achieve an adequate trade-off between the usage of EMBs and LUTs with respect to conventional FSM implementations based on ROM and to those based on LUT.

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Bit-Serial Logical Operation Processor Based on Shift Registers and Mealy Machine

Shen

2023

J. Phys.: Conf. Ser.

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With the rapid development of modern processors, logical operation processors could not only process data by logical operations but also store the data. The logical operation processor designed in this paper will be the bit-serial logical operation processor. In order to build the processor, four units should be designed first: the Shift Register Unit, Computation Unit, Routing Unit, and Control Unit. Among them, the Register Unit and the Control Unit are the most important. For the Register Unit, there will be two 4-bit registers. For the Control Unit, this circuit will implement a Mealy machine to determine the output and state of the circuit. The input to the processor will first get into the Control Unit, and then the data given outside will be stored in the Shift Register Unit and will be input to the Computation Unit and finally returned to the Shift Register Unit after Routing Unit. Since the processor is operating in series, the Control Unit and the Shift Register Unit should work synchronously.

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Structural Decomposition in FSM Design: Roots, Evolution, Current State—A Review

Cited by 15 publications

References 95 publications

Using Codes of Output Collections for Hardware Reduction in Circuits of LUT-Based Finite State Machines

Using Codes of Output Collections for Hardware Reduction in Circuits of LUT-Based Finite State Machines

Optimization based on the minimum maximal k-partial-matching problem of finite states machines with input multiplexing

Bit-Serial Logical Operation Processor Based on Shift Registers and Mealy Machine

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