On the mechanism of creating pinched hysteresis loops using a commercial memristor device

Majzoub, Sohaib; Elwakil, Ahmed S.; Psychalinos, Costas; Maundy, Brent

doi:10.1016/j.aeue.2019.152923

Cited by 20 publications

(24 citation statements)

References 17 publications

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“…Whereas, the fractional order memristor emulators given in the studies of Hamed et al (2018a), Hamed et al (2018b), Hamed et al (2019) generate either non-symmetrical lobes with two pinch-offs only (Hamed et al , 2018a; Hamed et al , 2018b) or else the operating frequency lies in the range of only few radians/sec, if four lobes are presented (Hamed et al , 2019). Moreover, unlike Biolek et al (2012a, 2012b) and Maizoub et al (2019), we have used pure sinusoidal signal (with no secondary harmonics) to generate the multi-lobe behaviour.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…In Biolek et al (2012a, 2012b) the cause of multiple lobe generation was considered as the multi-harmonic input, which was proved mathematically in the work. Experimental verification of this phenomena using commercially available conventional memristor IC has also been reported in Maizoub et al (2019). Several memristor models with their PHLs derived using static characteristics of memristor have been presented in Chua’s study (2015).…”

Section: Introductionmentioning

confidence: 95%

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Development of mathematical model and circuit emulators for four lobe memristive behaviour

Bhardwaj

Srivastava

2020

COMPEL

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Purpose This paper aims to develop a mathematical model for four-lobe memristor (FLM) element. The four-lobe memristive behaviour can be used in realization of hyperchaotic oscillators and implementation of multi-bit memories. For verification of the developed mathematical framework, two FLM circuit emulators have been presented using VDCC and IC LM13700, respectively. Design/methodology/approach A mathematical model for FLM has been developed in which, the condition for the existence of symmetrical four lobes, instances and coordinates of the end points of lobes has been derived and presented. Using this mathematical framework, a FLM emulator based on VDCC has been developed. To validate the possibility of practical implementation of FLM concept, an IC LM13700-based circuit has also been developed. The workability of VDCC based circuit has been verified by running simulations in PSPICE environment using CMOS VDCC model. Similarly, the behaviour of LM13700 IC-based circuit has been confirmed by SPICE model of LM13700 IC. Findings It has been shown mathematically that under certain conditions, third-order flux dependent equation of memductance can be used to generate four lobes on the transient v-i plane. Also, two FLM emulators without using any voltage multiplier circuit/IC have been reported. Originality/value From the best knowledge of the authors, there are no such FLM emulators that have been reported in literature so far, which operates at practical operating frequencies.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 95%

Development of mathematical model and circuit emulators for four lobe memristive behaviour

Bhardwaj

Srivastava

2020

COMPEL

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“…[6][7][8] They are all nonlinear, non-volatile, and nano-scale circuit components. 9 Meanwhile, the different circuits with memristive devices, [10][11][12] conventional components, and memory elements [13][14][15] were also analyzed. For example, W. Cai and R. Tetzlaff introduced a coupled relation and demonstrated multi-leaf and multi-pinched hysteresis loops in three coupled memristive systems; 10 D. Yu et al reported the dynamic behavior in dual coupled memristors in serial and parallel circuits; 12 L. Luo et al studied transient behaviors in multiple memristors, both in series and parallel connections; M. E. Fouda, A. G. Radwan and A. S. Elwakil proposed the model of inverse-memristor and a single equation that described series or parallel circuit models that containing a resistor (R), a capacitor (C), an inductor (L), and MRs 13,14 F. Corinto and M. Forti exploited the nonlinear dynamics and bifurcations of a circuit composed by a capacitor and a flux-controlled MR, [15][16][17] just to name a few.…”

Section: Introductionmentioning

confidence: 99%

“…Also, the concepts and models of MC and ML were extended and proposed 6‐8 . They are all nonlinear, non‐volatile, and nano‐scale circuit components 9 . Meanwhile, the different circuits with memristive devices, 10‐12 conventional components, and memory elements 13‐15 were also analyzed.…”

Section: Introductionmentioning

confidence: 99%

Nonlinear circuits with parallel‐/series‐connected HP‐type memory elements and their characteristic analysis

Liu

Guo

Chau

et al. 2021

Circuit Theory & Apps

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Summary In this paper, two nonlinear circuits are constructed based on the HP‐type flux‐/ charge‐controlled memory elements in parallel and series connections. Then, the phasor method is utilized to analyze and verify the frequency doubling mechanism between pinched hysteresis loops and the applied sinusoidal excitation. The expressions of equivalent admittance (denoted as YM) and impedance (denoted as ZM) for memory elements connected in parallel and series and the unified forms of which are also derived, respectively. Moreover, the mathematical models for the parallel‐/serial‐connected circuits are obtained and their characteristics are described. Meanwhile, the dual relationships, which come from the reciprocal relationship between YM and ZM, are also discovered based on their models. Furthermore, the gradual steady‐state oscillation and temporal behaviors are demonstrated for two nonlinear circuits. Finally, the experimental verification shows a good agreement between theoretical analysis and experimental results.

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“… Pinched hystersis is not a finger‐print of memristors only Pinched loops with lobe area widening (rather than declining) with increased frequency are possible and The existence of a non‐linearity is essential for generating this behaviour. This is because the theory of Lissajous figures necessitates the generation of a second‐harmonic frequency in the electrical current ( t ) when the applied voltage on the device v ( t ) has only one fundamental frequency (see [22] for a more detailed explanation) …”

Section: Introductionmentioning

confidence: 99%

Pinched hysteresis loops in non‐linear resonators

Elwakil

Fouda

Majzoub

et al. 2020

IET Circuits, Devices & Syst

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This study shows that pinched hysteresis can be observed in simple non‐linear resonance circuits containing a single diode that behaves as a voltage‐controlled switch. Mathematical models are derived and numerically validated for both series and parallel resonator circuits. The lobe area of the pinched loop is found to increase with increased frequency and multiple pinch points are possible with an odd‐symmetrical non‐linearity such as a cubic non‐linearity. Experiments have been performed to prove the existence of pinched hysteresis with a single diode and with two anti‐parallel diodes. The formation of a pinched loop in these circuits confirms the following: (1) pinched hysteresis is not a fingerprint of memristors, and (2) the existence of a non‐linearity is essential for generating this behaviour. Finally, an application in a digital logic circuit is validated.

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On the mechanism of creating pinched hysteresis loops using a commercial memristor device

Cited by 20 publications

References 17 publications

Development of mathematical model and circuit emulators for four lobe memristive behaviour

Development of mathematical model and circuit emulators for four lobe memristive behaviour

Nonlinear circuits with parallel‐/series‐connected HP‐type memory elements and their characteristic analysis

Pinched hysteresis loops in non‐linear resonators

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