On the Issues of Subnanometer EOT Gate Dielectric Scaling

High-k 2D Sb2O3 Made Using a Substrate-Independent and Low-Temperature Liquid-Metal-Based Process

“…16 Raman spectroscopy was carried out to confirm the crystal phase of as-synthesized 2D nanosheets using 532 nm excitation. α-Sb 2 O 3 is expected to feature active 2 A g , 2 E g , and 5 F 2g Raman modes. 16,30 As shown in Figure 3a,b, few layer thick 2D nanosheets feature sharp peaks at F 2g ∼ 188.5 cm −1 and A g ∼ 252.5 cm −1 , which are typical Raman modes of the αphase of Sb 2 O 3 , while thicker samples (∼20 nm) produced by repeated printing revealed additional peaks.…”

“…Insulating high- k dielectric nanosheets are an essential building block of 2D material-based and conventional electronics. − Dielectric materials are employed to improve capacitive coupling between metal and semiconductor contacts and minimize the leakage current between electrodes. − The suppression of leakage current is essential as it decreases energy consumption of digital electronics. − ,, This requirement renders high-quality dielectric materials that feature low defect densities critical for low-power electronics and ultrahigh integration circuits. ,− …”

“…As the dimensions of field-effect transistors (FETs) decrease toward a few nanometers of thicknesses, due to the continuing exponential growth of integration density of devices (Moore’s law), the thickness of the commonly used SiO 2 gate oxide is also required to shrink in order to boost performance. ,,,− However, the reduction of the insulating gate oxide to a few nanometers thickness leads to high leakage current, resulting in high energy consumption. ,,, To decrease power density, it is imperative to substitute SiO 2 with high dielectric constant (high -k ) metal oxide gate dielectrics which can handle leakage-free gate modulation independent of the thickness of the gate oxide. ,, …”

“…5−7 The suppression of leakage current is essential as it decreases energy consumption of digital electronics. [3][4][5]7,8 This requirement renders high-quality dielectric materials that feature low defect densities critical for low-power electronics and ultrahigh integration circuits. 2,9−13 As the dimensions of field-effect transistors (FETs) decrease toward a few nanometers of thicknesses, due to the continuing exponential growth of integration density of devices (Moore's law), the thickness of the commonly used SiO 2 gate oxide is also required to shrink in order to boost performance.…”

Demonstration of HfO2-Based Gate Dielectric With ~0.8-nm Equivalent Oxide Thickness on Si0.8Ge0.2 by Trimethylaluminum Pre-Treatment and Al Scavenger

“…However, IL thermal treatment and nitridation could not reach the equivalent oxide thickness (EOT) scaling less than 1 nm due to the thicker low-κ IL. As a result, to yield more drive current enhancement, the SiGe IL formation with low EOT and controlled leakage is highly desirable [13]. Recently, the SiGe gate stack composed of trimethylaluminum (TMA) interface treatment and in-situ high-dielectric Y 2 O 3 deposition was reported to demonstrate the EOT scaling down to 1 nm with ultralow D it , which could be attributed to the minimization of Ge-O bonds in SiGeO x ILs and the Y 2 O 3 thickness reduction [14], [15].…”