On the Interaction Between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays

Lamoureux, Julien; Wilton, Steven J. E.

doi:10.1166/jolpe.2005.023

Cited by 21 publications

(18 citation statements)

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“…Technology mapping and logic synthesis for FPGAs are well-studied, so we do not feel that future algorithms will provide significantly different LUT mappings, and hence result in significantly different conclusions. Power-aware mappers also exist [24,26,27], however, again we would not expect these to lead to significantly different conclusions. The heterogeneous technology mapping algorithm, SMAP, has a more significant impact on the results.…”

Section: Limitations Of This Studymentioning

confidence: 85%

“…Although it would be possible to perform the cut selection, output selection, or seed selection in a power-aware manner similar to [24], our experiments (not reported here) indicate that this does not work well. These methods helped to reduce routing energy slightly but did not address the large amounts of energy consumed by the memory blocks.…”

Section: Algorithm Enhancementmentioning

confidence: 90%

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On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays

Chin

Lee

Wilton

2008

International Journal of Reconfigurable Computing

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We investigate the power and energy implications of using embedded FPGA memory blocks to implement logic. Previous studies have shown that this technique provides extremely dense implementations of some types of logic circuits, however, these previous studies did not evaluate the impact on power. In this paper, we measure the effects on power and energy as a function of three architectural parameters: the number of available memory blocks, the size of the memory blocks, and the flexibility of the memory blocks. We show that although embedded memories provide area efficient implementations of many circuits, this technique results in additional power consumption. We also show that blocks containing smaller-memory arrays are more power efficient than those containing large arrays, but for most array sizes, the memory blocks should be as flexible as possible. Finally, we show that by combining physical arrays into larger logical memories, and mapping logic in such a way that some physical arrays can be disabled on each access, can reduce the power consumption penalty. The results were obtained from place and routed circuits using standard experimental physical design tools and a detailed power model. Several results were also verified through current measurements on a 0.13 μm CMOS FPGA.

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Section: Limitations Of This Studymentioning

confidence: 85%

Section: Algorithm Enhancementmentioning

confidence: 90%

On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays

Chin

Lee

Wilton

2008

International Journal of Reconfigurable Computing

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“…Placing logic blocks on a critical-path close together minimizes delay and placing logic blocks connected by many wires close together improves power and routability. Power can be further minimized by assigning more weight to connections with high toggle rates, as described in [Lamoureux 2005]. For applications with many clock domains, however, constraints that limit the number of clock nets within ribs (W rib ) and within a region (W local ) can interfere with these optimizations.…”

Section: Clock-aware Placementmentioning

confidence: 99%

“…A suite of benchmark circuits is implemented on a user-specified FPGA architecture using standard academic FPGA CAD tools. The CAD tools consist of the Emap technology mapper [Lamoureux 2005], the T-VPack clusterer [Betz 1999], the VPR placer (with clock-aware enhancements), and the VPR router [Betz 1999]. Note that the T-VPack does not need to be enhanced since it is already clock-aware.…”

Section: Experimental Frameworkmentioning

confidence: 99%

On the trade-off between power and flexibility of FPGA clock networks

Lamoureux

Wilton

2008

ACM Trans. Reconfigurable Technol. Syst.

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________________________________________________________________________FPGA clock networks consume a significant amount of power since they toggle every clock cycle and must be flexible enough to implement the clocks for a wide range of different applications. The efficiency of FPGA clock networks can be improved by reducing this flexibility; however, reducing the flexibility introduces stricter constraints during the clustering and placement stages of the FPGA CAD flow. These constraints can reduce the overall efficiency of the final implementation. This paper examines the tradeoff between the power consumption and flexibility of FPGA clock networks.Specifically, this paper makes three contributions. First, it presents a new parameterized clock network framework for describing and comparing FPGA clock networks. Second, it describes new clock-aware placement techniques that are needed to find a legal placement that satisfies the constraints imposed by the clock network. Finally, it performs an empirical study to examine the tradeoff between the power consumption of the clock network and the impact of the CAD constraints for a number of different clock networks with varying amounts of flexibility.The results show that the techniques used to produce a legal placement can have a significant influence on power and the ability of the placer to find a legal solution. On average, circuits placed using the most effective techniques dissipate 5% less overall energy and were significantly more likely to be legal than circuits placed using other techniques. Moreover, the results show that the architecture of the clock network is also important. On average, FPGAs with an efficient clock network were up to 14.6% more energy efficient compared to other FPGAs. Permission to make digital/hard copy of part of this work for personal or classroom use is granted without fee provided that the copies are not made or distributed for profit or commercial advantage, the copyright notice, the title of the publication, and its date of appear, and notice is given that copying is by permission of the ACM, Inc. To copy otherwise, to republish, to post on servers, or to redistribute to lists, requires prior specific permission and/or a fee. © 2008 ACM 1073-0516/01/0300-0034 $5.00Designing a suitable clock distribution network for an FPGA is significantly more challenging than designing such a network for a fixed function chip such as an Application-Specific Integrated Circuit (ASIC). In an ASIC, the locations and skew requirements of each domain are known when the clock network is designed. In an FPGA, however, a single clock network that works well across many applications must be created. When the FPGA is designed, the number of clock domains the user will require, the clock signals that will be generated, the skew requirements of each domain, and where each domain will be located on the chip are all unknown. This forces FPGA vendors to create very complex yet flexible clock distribution circuitry.This flexibility has a significant area a...

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“…As we know, routing power plays a significant part of power consumption of modern FPGAs. And among routing power, global routing power is much larger than local routing power since longer global routing tracks and switches introduce larger parasitic capacitance [3]. Therefore, if we can alleviate the usage of global routing resources, we can reduce the power.…”

Section: Introductionmentioning

confidence: 99%

A low power technology mapping method for Adaptive Logic Module

Chen

Zhang

Yoshimura

et al. 2011

2011 International Conference on Field-Programmable Technology

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In this paper, we propose a novel mapping method for FPGA with dual-output LUT based logic elements (LEs), aiming for power reduction. Recently, a new kind of LE-Adaptive Logic Module (ALM), which contains a dual-output fracturable LUT instead of traditional single-output K-LUT, is used in Altera's high-end FPGA products to obtain a good trade-off between area and delay. To map a design to ALMs, we introduce a LUT-merging step after K-LUT technology mapping, where the LUTs are merged into ALMs. We propose a max-weight matching based method for the LUT-merging, trying to reduce the number of used ALMs and meanwhile reduce power consumption. Experimental results show that, compared with a previous LUT-merging method for area-optimization, though resulting in a little more ALMs, our low power LUT-merging method improves the power by 7.48%.

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On the Interaction Between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays

Cited by 21 publications

References 50 publications

On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays

On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays

On the trade-off between power and flexibility of FPGA clock networks

A low power technology mapping method for Adaptive Logic Module

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