On the Growth of the Prime Numbers Based Encoded Vector Clock

Kshemkalyani, Ajay D.; Voleti, Bhargav

doi:10.1007/978-3-030-05366-6_14

Cited by 2 publications

(3 citation statements)

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“…The main drawback of the EVC has been shown to be the extremely high growth rate which quickly causes an overflow at the locations that are storing the EVC values [9]. By relying on multiplications and least common multiple operations, EVC values grow at an exponential rate, which can quickly require a very large number of bits in order to be able to represent it, and therefore store it.…”

Section: Related Workmentioning

confidence: 99%

“…The REVC is built on the EVC and internally makes use of EVC values and operations to implement the logical clock. The EVC has been shown to have exponential growth, due to its use of multiplication and least common multiple (LCM) operations [7], [9]. However, the REVC introduces the use of a reset operation that does not allow the EVC value to grow past a certain number of bits.…”

Section: Growth Ratementioning

confidence: 99%

“…The EVC is a technique to represent a Vector Clock using a single scalar number, to improve scalability of the VC and it is based on the use of prime numbers to achieve such encoding. The main drawback of the EVC has been shown to be the extremely high growth rate which quickly causes an overflow at the locations that are storing the EVC values [9].…”

Section: Introductionmentioning

confidence: 99%

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Resettable Encoded Vector Clock for Causality Analysis With an Application to Dynamic Race Detection

Pozzetti

Kshemkalyani

2021

IEEE Trans. Parallel Distrib. Syst.

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Causality tracking among events is a fundamental challenge in distributed environments. Much previous work on this subject has focused on designing an efficient and scalable protocol to represent logical time. Several implementations of logical clocks have been proposed, most recently the Encoded Vector Clock (EVC), a protocol to encode Vector Clocks (VC) in scalar numbers through the use of prime numbers, to improve performance and scalability. We propose and formalize the concept of Resettable Encoded Vector Clock (REVC), a new logical clock implementation, which builds on the EVC to tackle its very high growth rate issue. We show how our REVC can be applied in both shared memory systems and message passing systems to achieve a consistent logical clock. We show, through practical examples, the advantage of REVC's growth rate with respect to EVC's growth rate. Finally, we show a practical application of the REVC to the dynamic race detection problem in multi-threaded environments. We compare our tool to the currently existing VC-based tool DJIT + to show how the REVC can help in achieving higher performance with respect to the Vector Clock.

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Section: Related Workmentioning

confidence: 99%

Section: Growth Ratementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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