On the generation of multiplexer circuits for pass transistor logic

Scholl, Christoph; Becker, Bernd

doi:10.1145/343647.343800

Cited by 21 publications

(25 citation statements)

References 15 publications

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“…Note that only 1s and 0s are fed into the multiplexers (the analog of the Shannon's expansion shown in Figure 1). This strategy allows the implementation of the synthesized circuits by means of pass transistor logic (Scholl et al 2000). The design metric driving the implementation is the number of components.…”

Section: Problem Statementmentioning

confidence: 99%

Evolutionary Synthesis of Logic Circuits Using Information Theory

Aguirre

Coello

2004

Artificial Intelligence in Logic Design

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Abstract. In this paper, we propose the use of Information Theory as the basis for designing a fitness function for Boolean circuit design using Genetic Programming. Boolean functions are implemented by replicating binary multiplexers. Entropy-based measures, such as Mutual Information and Normalized Mutual Information are investigated as tools for similarity measures between the target and evolving circuit. Three fitness functions are built over a primitive one. We show that the landscape of Normalized Mutual Information is more amenable for being used as a fitness function than simple Mutual Information. The evolutionary synthesized circuits are compared to the known optimum size. A discussion of the potential of the Information-Theoretical approach is given.

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Section: Problem Statementmentioning

confidence: 99%

Evolutionary Synthesis of Logic Circuits Using Information Theory

Aguirre

Coello

2004

Artificial Intelligence in Logic Design

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“…a sifting modification targeting the classical criterion for circuit speed, the maximal delay on a critical path, as well as the standard sifting algorithm targeting BDD size to circuits of the LGSynth93 [13] benchmark set. A weaker form of MPL sifting with a simplified cost function has been used in [20]. Since we are interested in a validation of the quality of results yielded by EPL sifting, we implemented a sifting modification targeting the classical MPL criterion.…”

Section: Resultsmentioning

confidence: 99%

“…every gate (which is corresponding to a BDD node) is assigned a uniform delay of one. This model is independent of the technology used and has been applied to the unmapped netlists in the synthesis approach of [20]. Then, the EPL models average gate delay for PTL networks derived from BDDs: EPL accounts for the fact…”

Section: Applying the Expected Path Length In Logic Synthesismentioning

confidence: 99%

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Minimization of the expected path length in BDDs based on local changes

Ebendt¹,

Gunther²,

Drechsler³

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

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Abstract-In many verification tools methods for functional simulation based on reduced ordered Binary Decision Diagrams (BDDs) are used. The evaluation time for a BDD can be crucial and is measured by the expected path length of the BDD.In this paper a new technique for BDD minimization with respect to the expected path length is suggested to reduce evaluation time. It is based on sifting and, unlike previous approaches, performs variable swaps with the same time complexity as the original sifting algorithm.Another field of application for BDDs is logic synthesis, often targeting Pass Transistor Logic (PTL) because of low power and low cost. A minimization of BDD size and chip area can lead to poor timing performances. We suggest to also use our method here, as the resulting BDDs show a very low maximal and average path delay. This supports the synthesis of high-speed PTL circuits at low area overhead.Experimental results are given to show the efficiency of our approach.

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“…Second, the longest path in the BDD corresponds to the critical path in a derived circuit. Hence minimization with respect to MPL/EPL is expected to support synthesis approaches targeting the delay of the resulting circuits [13]. The minimization of MPL has been studied in [10], [14].…”

Section: Introductionmentioning

confidence: 99%

On the sensitivity of BDDs with respect to path-related objective functions

Ebendt

Drechsler

2006 IEEE International Symposium on Circuits and Systems

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Abstract-Reduced ordered Binary Decision Diagrams (BDDs) are a data structure for efficient representation and manipulation of Boolean functions. They are frequently used in logic synthesis and formal verification. In recent practical applications, BDDs are optimized with respect to new objective functions. In 1986, Bryant showed that, dependent on a chosen variable ordering, the size of BDDs can vary from linear to exponential. In this paper we derive similar results for the sensitivity of BDDs with respect to path-related objective functions. First, we provide a theoretical view, giving examples for the large variation in the maximal path length and the expected path length in BDDs. This shows how important it is to choose a good or optimal variable ordering. Experimental results show the sensitivity of benchmark functions with respect to all considered objective functions.

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On the generation of multiplexer circuits for pass transistor logic

Cited by 21 publications

References 15 publications

Evolutionary Synthesis of Logic Circuits Using Information Theory

Evolutionary Synthesis of Logic Circuits Using Information Theory

Minimization of the expected path length in BDDs based on local changes

On the sensitivity of BDDs with respect to path-related objective functions

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