On the Forward Bias Excess Capacitance at Intimate and MIS Schottky Barrier Diodes with Perfect or Imperfect Ohmic Back Contact

Abstract

An experimental explanation of the forward bias Capacitance-frequency plots for intimate or MIS SBDs with perfect or imperfect ohmic back-contact has been made. It has been shown that there is no excess capacitance that could be ascribed to the interface states or minority carrier at the intimate SBDs (that is, without interfacial layer) with the perfect ohmic back contact (low-resistance). It has been found that the excess capacitance is only measurable at SBDs with imperfect back contacts or with an interfacial layer which separates the interface states from the metal. It has been found that excess capacitance can be generated by varying the resistance or quality of the back-ohmic contact to the bulk semiconductor substrate, that is, the density of minority carriers that are injected by the Schottky contact depends sensitively on the properties of the ohmic back-contact. Again, it has been seen that the excess capacitance has appeared owing to the interface states plus minority carriers in MIS SBDs with imperfect back contacts. Thus, it has been concluded that the excess capacitance at nonideal Schottky contacts has been caused not only by the interface states but also by the minority carriers or by the interface states plus minority carriers due to the poor frontside or poor backside contacts. Thereby, it has been experimentally shown that every forward bias C-f plots with excess capacitance cannot be used to extract the results related to the interface states.

The physics and chemistry of the Schottky barrier height

“…There are also other pitfalls with C-V measurements that should be avoided. 151,152 Because of the exponential dependence of the magnitude of junction current on the SBH, exp½ÀU B =ðk B TÞ, I-V measurement is dominated by the portions of the MS interface with lower-thanaverage SBH; and the lower the measurement temperature, the more pronounced the dominance of the low SBH patches. The upper-half of the SBH distribution of an MS interface is not accessible experimentally by I-V measurements, except by special techniques with spatial resolution such as BEEM or electron-beam induced conduction (EBIC).…”

Electrical and Photoconductivity Properties of Al/CdFe2O4/p-Si/Al Photodiode

“…The interface states are very sensitive to the AC signal at low frequency, but their sensitivity is reduced at high frequency. This may also explain the observed reduction of the capacitance at higher frequencies [19]. Since charge trapped at the defects that may be formed at grain boundaries, around the contacts or at the metallurgic junction between Si and CdFe 2 O 4 used to form the device, can lead to space charge distribution, hence strong frequency dependence can also be related to various defects.…”

“…To correct for the effect of series resistance on the capacitance and conductance, the following equations can be used [19][20][21][22]:…”

“…For the former the intersection of the resulting curve on the voltage axis is sufficient. For space charge density ( ) the slope of the plot can be fitted to the following relationship [16,[19][20][21][22][23][24]:…”

Capacitance-Voltage (C-V) Characteristics of Cu/n-type InP Schottky Diodes

“…The increase in the G/ω value at a low frequency can be explained by the increase in the number of charge carriers available for a given relaxation time of the interface states [5]. In Au/n-Si Schottky diodes, Bati et al observed an excess capacitance arising from the diffusion of minority carriers and they explained that the presence of an interfacial layer at the MS interface increased the capacitance with decreasing frequency due to the interface states [25]. Therefore, such C and G/ω behaviors with applied bias voltage and frequency can result from the influence of interface states.…”