On the Exploration of the Solution Space in Analog Placement With Symmetry Constraints

Balasa, Florin; Maruvada, S.C.; Krishnamoorthy, Karthik

doi:10.1109/tcad.2003.822132

Cited by 61 publications

(68 citation statements)

References 26 publications

(52 reference statements)

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“…Table VI lists the names of the industry benchmark circuits, the total areas, and the runtime for SPs, segment trees, SPs with linear programming, SPs with dummy nodes, and HB * -tree. The results show that our algorithm achieved average area reductions of 7.1%, 6.6%, 1.6%, and 10.3% over [8], [12], [16], and [17], respectively. In some applications, the orientations of analog device modules may not be allowed to be changed.…”

Section: Resultsmentioning

confidence: 96%

“…We performed two sets of experiments: One is based on the four MCNC benchmarks (apte, hp, ami33, and ami49) used in [15], and the other consists of two real industry analog designs (biasynth_2p4g and lnamixbias_2p4g) used in [12] and [16] (note that they both were extracted by Koda et al [16] from [12,Figs. 9 and 10]).…”

Section: Resultsmentioning

confidence: 99%

“…In the second set of experiments, we compared our algorithm with SPs in [8], segment trees in [12], SPs with linear programming in [16], and SPs with dummy nodes in [17]. Table VI lists the names of the industry benchmark circuits, the total areas, and the runtime for SPs, segment trees, SPs with linear programming, SPs with dummy nodes, and HB * -tree.…”

Section: Resultsmentioning

confidence: 99%

“…Balasa et al derived the symmetric-feasible conditions for several popular floorplan representations including sequence pairs (SPs) [8], O-tree [9], and binary trees [10]. To explore the solution space in the symmetric-feasible binary trees, they augmented the B * -tree [11] using various data structures, including segment trees [3], [12], red-black trees [13], and deterministic skip lists [14]. Lin et al [15] also presented the symmetric-feasible conditions for the TCG-S representation.…”

Section: A Previous Workmentioning

confidence: 99%

“…Specifically, the packing complexity of the previous works [8]- [10], [15]- [17], [19] are all O(n 2 ) time while those of [3], [12]- [14] need O(n lg n) time (the work in [18] requires O(m · n lg lg n) time, which was the fastest previous work).…”

Section: B Our Contributionsmentioning

confidence: 99%

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Analog Placement Based on Symmetry-Island Formulation

Lin

Chang

Lin³

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-To reduce the effect of parasitic mismatches and circuit sensitivity to thermal gradients or process variations for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis, and the symmetric modules are preferred to be placed at closest proximity for better electrical properties. Most previous works handle the problem with symmetry constraints by imposing symmetric-feasible conditions in floorplan representations and using cost functions to minimize the distance between symmetric modules. Such approaches are inefficient due to the large search space and cannot guarantee the closest proximity of symmetry modules. In this paper, we present the first linear-time-packing algorithm for the placement with symmetry constraints using the topological floorplan representations. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected placement. Based on this concept and the B * -tree representation, we propose automatically symmetric-feasible (ASF) B * -trees to directly model the placement of a symmetry island. We then present hierarchical B * -trees (HB * -trees) which can simultaneously optimize the placement with both symmetry islands and nonsymmetric modules. Unlike the previous works, our approach can place the symmetry modules in a symmetry group in close proximity and significantly reduce the search space based on the symmetry-island formulation. In particular, the packing time for an ASF-B * -tree or an HB * -tree is the same as that for a plain B * -tree (only linear) and much faster than previous works. Experimental results show that our approach achieves the best-published quality and runtime efficiency for analog placement.

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Section: Resultsmentioning

confidence: 96%

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: A Previous Workmentioning

confidence: 99%

Section: B Our Contributionsmentioning

confidence: 99%

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Analog Placement Based on Symmetry-Island Formulation

Lin

Chang

Lin³

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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A hybrid evolutionary analogue module placement algorithm for integrated circuit layout designs

Zhang

Raut

Jiang

et al. 2005

Int. J. Circ. Theor. Appl.

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SUMMARYThis paper presents an integrated approach of simulated annealing (SA) and genetic algorithm (GA) for the analogue module placement in mixed-signal integrated circuit layout designs. The proposed algorithm follows the optimization ow of a normal GA controlled by the methodology of SA. The bitmatrix chromosomal representation is employed to describe the location and the orientation of modules. Compared with the conventional bit-string representation, the proposed chromosomal representation tends to signiÿcantly improve the search e ciency. In addition, a slide-based at scheme is developed to transform an absolute co-ordinate placement of modules to a relative placement. In this way, the symmetry constraints imposed on analogue very large scale integration circuits can be easily fulÿlled in the placement run. Use of a radiation-decoder can also drastically shrink the conÿguration space without degrading search opportunities. The proposed algorithm has been tested with several example circuits. The experiments show this promising algorithm makes the better performance than the simpler SA or GA approaches working alone, and the quality of the automatically generated layouts is comparable to those done manually.

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Symmetry‐aware placement algorithm using transitive closure graph representation for analog integrated circuits

Zhang

Jiang

et al. 2008

Circuit Theory & Apps

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SUMMARYRecently several topological representations have been explored as alternatives to the conventional absolute-coordinate representation for integrated circuit layout automation. Those topological representations, however, lack one or more aspects in capturing the solution space subject to symmetry constraints, which are abundant in analog layouts.In this paper, we explore the use of transitive closure graphs (TCGs) to represent analog placements, i.e. placements with symmetry constraints. We define a set of conditions so that a TCG satisfying these conditions, referred to as a symmetric-feasible TCG, will correspond to a valid symmetric placement and vice versa. We then present an O(n 2 ) algorithm, where n is the number of cells to be placed, to build a symmetric placement from a symmetric-feasible TCG, a problem known as packing.We further describe a set of random perturbation operations on existing symmetric-feasible TCGs to generate new symmetric-feasible TCGs with time complexity of O(n). This allows our TCG-based symmetry-aware analog placer to search only the symmetric-feasible TCG solution space, leading to a substantial reduction of the search space and solution time. Experimental results on several analog circuits have confirmed the superiority of the TCG representation to the conventional absolute-coordinate representation as well as several other topological representations in analog layout design.

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On the Exploration of the Solution Space in Analog Placement With Symmetry Constraints

Cited by 61 publications

References 26 publications

Analog Placement Based on Symmetry-Island Formulation

Analog Placement Based on Symmetry-Island Formulation

A hybrid evolutionary analogue module placement algorithm for integrated circuit layout designs

Symmetry‐aware placement algorithm using transitive closure graph representation for analog integrated circuits

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