On the Elements of High Throughput Cu-CMP Slurries Compatible with Low Step Heights

Kanki, Tsuyoshi; Shirasu, T.; Takesako, S.; Sakamoto, M.; Asneil, A.; Idani, Naoki; Kimura, Takahiro; Nakamura, Tomoji; Miyajima, M.

doi:10.1109/iitc.2008.4546931

Cited by 9 publications

(5 citation statements)

References 2 publications

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“…The COFs measured during nanoscratching ͑ = 0.3-0.6͒ are similar to measurements with alumina and oxide slurries in contact with Cu. 48,50 It is estimated that the Cu reaction layer, when exposed to solutions for long durations, is on the order of 5 nm in thickness, 51 as was observed in pH 9 slurries in contact with Cu, 52 which is consistent with our result. Enhanced material removal during imaging was also observed for the carbon-doped oxide LK materials, which is expected at high pH.…”

Section: ͓15͔supporting

confidence: 91%

Nanoscale Defect Generation in CMP of Low-k/Copper Interconnect Patterns

Choi

Korach

2009

J. Electrochem. Soc.

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Chemical mechanical polishing ͑CMP͒ can lead to nanoscale damage in films and surface features due to normal and lateral deformations of the surface. Defects arise due to the synergistic effects of chemical and mechanical mechanisms. This occurrence increases with severity as feature sizes are on the same order as abrasive polishing particles and materials decrease in stiffness, as with advanced low-k dielectrics. Here, relationships describing the response of normal and lateral surface deformations have been developed experimentally and from contact modeling. This is achieved by atomic force microscopy nanoscratching with diamond tips in a KOH environment to simulate CMP processing conditions. The deformations are related to the applied normal load, friction coefficient, film properties, and line densities. The deformations are observed to have critical loads of 1 and 5 N associated with normal and lateral deformations, respectively, which are on the same order as actual CMP particle pressure estimates.There exists an ever increasing need in the semiconductor industry to reduce the size of an integrated circuit ͑IC͒ while improving its performance. This has been achieved by producing multilevel structures and using advanced materials. 1 With the use of layered structures, the formation of nonplanarized surface topography during fabrication is a challenge. Chemical mechanical polishing ͑CMP͒ has been developed intensively and has shown a dynamic growth, playing a key role in the semiconductor industry because it is not only an efficient planarization process but also an effective way of removing wafer surface defects. CMP has allowed the improved lateral circuit dimensions to minimize interconnect delay, 2 and the minimization process has been achieved by the transition from aluminum to copper metal interconnects and from traditional dielectric SiO 2 to low-k ͑LK͒ or ultralow-k ͑ULK͒ dielectric materials. 3 However, the adoption of porous LK materials has brought implementation problems, such as delamination of dielectric materials during CMP due to poor adhesion between layers, poor mechanical strength of porous LK interlayer dielectrics, 4 low thermal conductivity, and incompatibility with existing IC manufacturing processes. 5,6 The formation of surface defects on LK interlayer dielectrics during CMP affects local, near-neighbor structures as well as multilevel structures after subsequent process steps, leading to decreased reliability and performance degradation.Many researchers have worked to investigate LK dielectric material delamination and wear. 7-14 Busch and Hosali 15 observed structural and chemical modifications of LK materials due to CMP operating conditions, whereas Balakumar et al. 16 performed CMP on Cu/SiLK single-and dual-stack nonpatterned wafers to study fundamentals of delamination during CMP, and Leduc et al. 17 measured the dependence of CMP-induced delamination on LK dielectric film stacks and established a relationship between delamination and the number of ULK dielectric layers.In addit...

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Section: ͓15͔supporting

confidence: 91%

Nanoscale Defect Generation in CMP of Low-k/Copper Interconnect Patterns

Choi

Korach

2009

J. Electrochem. Soc.

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“…Moreover, cracks, delamination, scratching and contamination are the problems accompanied with Cu CMP process because the Cu CMP process is basically a frictional process. These problems can be solved through: (i) reducing the down-force during Cu CMP process; (ii) improving the adhesion between layers in the interconnect; (iii) optimizing the used slurry; (iv) depositing a relatively dense material, such as SiO 2 or nonporous SiCOH films on the top of the porous low-k dielectric film; and (v) performing an optimized wetting clean after the CMP process [70][71][72].…”

Section: Cu Chemical Mechanical Polishingmentioning

confidence: 99%

Copper Metal for Semiconductor Interconnects

Cheng¹,

Lee²,

Huang³

2018

Noble and Precious Metals - Properties, Nanoscale Effects and Applications

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Resistance-capacitance (RC) delay produced by the interconnects limits the speed of the integrated circuits from 0.25 mm technology node. Copper (Cu) had been used to replace aluminum (Al) as an interconnecting conductor in order to reduce the resistance. In this chapter, the deposition method of Cu films and the interconnect fabrication with Cu metallization are introduced. The resulting integration and reliability challenges are addressed as well.

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“…The wafers are placed face-down on a rotating pad on which the slurry is dispensed. In addition, low downforce processes are required to minimize Cu erosion during the overpolish step [103]. The first step is Cu removal, stopping on the barrier layer, and the second step is the barrier removal, stopping on the dielectric.…”

Section: Chemical Mechanical Polishingmentioning

confidence: 99%

Process Technology for Copper Interconnects

Gambino

2012

Handbook of Thin Film Deposition

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On the Elements of High Throughput Cu-CMP Slurries Compatible with Low Step Heights

Cited by 9 publications

References 2 publications

Nanoscale Defect Generation in CMP of Low-k/Copper Interconnect Patterns

Nanoscale Defect Generation in CMP of Low-k/Copper Interconnect Patterns

Copper Metal for Semiconductor Interconnects

Process Technology for Copper Interconnects

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