On the Effectiveness of the Satisfiability Attack on Split Manufactured Circuits

Chen, Suyuan; Vemuri, Ranga

doi:10.1109/vlsi-soc.2018.8644963

Cited by 9 publications

(14 citation statements)

References 12 publications

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“…Attacks using proximity information as a metric are not the only solution to recover missing BEOL connections. An effective methodology to apply a Boolean satisfiability based strategy is proposed by Chen et al [22]. The authors claim that their attack methodology does not need (or depend on) any proximity information, or even any other insights into the nature of EDA tools utilized in the design process.…”

Section: Attacks On Split Manufacturingmentioning

confidence: 99%

“…In reality, [22] presents a different interpretation of Threat model I since the attacker is assumed to possess a functional IC. This IC would then have to be available in the open market for the attacker to be able to purchase it.…”

Section: Attacks On Split Manufacturingmentioning

confidence: 99%

“…Experimental results presented by [22] utilize ISCAS'85 and ITC'99 benchmark circuits. It has been shown that their attack could recover a logically correct netlist for all the studied circuits.…”

Section: Attacks On Split Manufacturingmentioning

confidence: 99%

“…In order to increase the efficiency and capacity of the SAT attack proposed in [22], the authors proposed two improvements in [23]. First, the size of the key-controlled interconnect network that models the possible BEOL connections is reduced.…”

Section: Attacks On Split Manufacturingmentioning

confidence: 99%

See 3 more Smart Citations

A Survey on Split Manufacturing: Attacks, Defenses, and Challenges

Perez

Pagliarini

2020

IEEE Access

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In today's integrated circuit (IC) ecosystem, owning a foundry is not economically viable, and therefore most IC design houses are now working under a fabless business model. In order to overcome security concerns associated with the outsorcing of IC fabrication, the Split Manufacturing technique was proposed. In Split Manufacturing, the Front End of Line (FEOL) layers (transistors and lower metal layers) are fabricated at an untrusted high-end foundry, while the Back End of Line (BEOL) layers (higher metal layers) are manufactured at a trusted low-end foundry. This approach hides the BEOL connections from the untrusted foundry, thus preventing overproduction and piracy threats. However, many works demonstrate that BEOL connections can be derived by exploiting layout characteristics that are introduced by heuristics employed in typical floorplanning, placement, and routing algorithms. Since straightforward Split Manufacturing may not afford a desirable security level, many authors propose defense techniques to be used along with Split Manufacturing. In our survey, we present a detailed overview of the technique, the many types of attacks towards Split Manufacturing, as well as possible defense techniques described in the literature. For the attacks, we present a concise discussion on the different threat models and assumptions, while for the defenses we classify the studies into three categories: proximity perturbation, wire lifting, and layout obfuscation. The main outcome of our survey is to highlight the discrepancy between many studiessome claim netlists can be reconstructed with near perfect precision, while others claim marginal success in retrieving BEOL connections. Finally, we also discuss future trends and challenges inherent to Split Manufacturing, including the fundamental difficulty of evaluating the efficiency of the technique.

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Section: Attacks On Split Manufacturingmentioning

confidence: 99%

Section: Attacks On Split Manufacturingmentioning

confidence: 99%

Section: Attacks On Split Manufacturingmentioning

confidence: 99%

Section: Attacks On Split Manufacturingmentioning

confidence: 99%

See 2 more Smart Citations

A Survey on Split Manufacturing: Attacks, Defenses, and Challenges

Perez

Pagliarini

2020

IEEE Access

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“…Another variation of the threat model was explored by Chen and Vemuri [78]. The authors assume that a working chip is available which is then used as an oracle for a SAT-based formulation to recover the missing BEOL connections.…”

Section: Threat Modelmentioning

confidence: 99%

Protect Your Chip Design Intellectual Property

Knechtel

Patnaik

Sinanoglu

2019

Proceedings of the International Conference on Omni-Layer Intelligent Systems

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The increasing cost of integrated circuit (IC) fabrication has driven most companies to "go fabless" over time. The corresponding outsourcing trend gave rise to various attack vectors, e.g., illegal overproduction of ICs, piracy of the design intellectual property (IP), or insertion of hardware Trojans (HTs). These attacks are possibly conducted by untrusted entities residing all over the supply chain, ranging from untrusted foundries, test facilities, even to end-users. To overcome this multitude of threats, various techniques have been proposed over the past decade. In this paper, we review the landscape of IP protection techniques, which can be classified into logic locking, layout camouflaging, and split manufacturing. We discuss the history of these techniques, followed by state-of-the-art advancements, relevant limitations, and scope for future work. CCS CONCEPTS• Security and privacy → Security in hardware;

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Satisfiability Based Attacks

Vemuri

Chen

2021

Split Manufacturing of Integrated Circuits for Hardware Security and Trust

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On the Effectiveness of the Satisfiability Attack on Split Manufactured Circuits

Cited by 9 publications

References 12 publications

A Survey on Split Manufacturing: Attacks, Defenses, and Challenges

A Survey on Split Manufacturing: Attacks, Defenses, and Challenges

Protect Your Chip Design Intellectual Property

Satisfiability Based Attacks

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