On the design of the local variable cache in a hardware translation-based java virtual machine

Oi, Hitoshi

doi:10.1145/1065910.1065923

Cited by 3 publications

(2 citation statements)

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“…If the part of operand stack for the local variables is allocated on the main memory (which is likely as shown in the example in Table 1), the instruction folding is not possible. Previously, we proposed to add a small register file to the datapath of the JVM to reduce the number of memory accesses caused by the local variables [7]. This extra register file (called local variable cache in [7]) also makes instruction folding possible on the hardware-translation based JVMs.…”

Section: Instruction Folding Of Java Bytecodementioning

confidence: 99%

Instruction folding in a hardware-translation based java virtual machine

2006

Proceedings of the 3rd Conference on Computing Frontiers

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Bytecode hardware-translation improves the performance of a Java Virtual Machine (JVM) with small hardware resource and complexity overhead. Instruction folding is a technique to further improve the performance of a JVM by reducing the redundancy in its stack-based operations. However, the variable instruction length of the Java bytecode makes the folding logic complex. In this paper, we propose a folding scheme with reduced hardware complexity and evaluate its performance. For eleven benchmark cases, the proposed scheme folded 7.1% to 36.8% of the bytecodes which correspond to 74.0% to 99.7% of the PicoJava-II's folding performance.

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Section: Instruction Folding Of Java Bytecodementioning

confidence: 99%

Instruction folding in a hardware-translation based java virtual machine

2006

Proceedings of the 3rd Conference on Computing Frontiers

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“…This paper describes work carried out with the goal of developing a low power Maté compliant VM suitable for WSN motes. In common with previous work on embedded Java Virtual Machines (JVMs) [6,7], the approach taken is to provide hardware support for various aspects of the VM, thus migrating certain components of the VM from software to hardware. Clearly, a naive porting of the entire software VM to hardware would provide an expensive solution in terms of silicon area and cost.…”

Section: Introductionmentioning

confidence: 99%

Towards a Low Power Virtual Machine forWireless Sensor Network Motes

Bleakley

2006

2006 Japan-China Joint Workshop on Frontier of Computer Science and Technology

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Virtual Machines (VMs) have been proposed as an efficient programming model for Wireless Sensor Network (WSN) devices. However, the processing overhead required for VM execution has a significant impact on the power consumption and battery lifetime of these devices. This paper analyses the sources of power consumption in the Maté VM for WSNs. The paper proposes a generalised processor architecture allowing for hardware acceleration of VM execution. The paper proposes a number of hardware accelerators for Maté VM execution and assesses their effectiveness.

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The Javelin: A Java accelerator based on hardware translation method

Lee¹,

Kim²

2008

2008 International SoC Design Conference

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On the design of the local variable cache in a hardware translation-based java virtual machine

Cited by 3 publications

References 1 publication

Instruction folding in a hardware-translation based java virtual machine

Instruction folding in a hardware-translation based java virtual machine

Towards a Low Power Virtual Machine forWireless Sensor Network Motes

The Javelin: A Java accelerator based on hardware translation method

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