Instruction folding in a hardware-translation based java virtual machine

Abstract

Bytecode hardware-translation improves the performance of a Java Virtual Machine (JVM) with small hardware resource and complexity overhead. Instruction folding is a technique to further improve the performance of a JVM by reducing the redundancy in its stack-based operations. However, the variable instruction length of the Java bytecode makes the folding logic complex. In this paper, we propose a folding scheme with reduced hardware complexity and evaluate its performance. For eleven benchmark cases, the proposed scheme folded 7.1% to 36.8% of the bytecodes which correspond to 74.0% to 99.7% of the PicoJava-II's folding performance.

JavaFlow — A Java dataflow machine

“…Other efforts continued to seek optimizations on the execution of ByteCodes by eliminating, reordering, and translating ByteCode instructions [14][15][16].…”

Towards a Low Power Virtual Machine forWireless Sensor Network Motes

“…This paper describes work carried out with the goal of developing a low power Maté compliant VM suitable for WSN motes. In common with previous work on embedded Java Virtual Machines (JVMs) [6,7], the approach taken is to provide hardware support for various aspects of the VM, thus migrating certain components of the VM from software to hardware. Clearly, a naive porting of the entire software VM to hardware would provide an expensive solution in terms of silicon area and cost.…”