On the Design of Low-Power Hybrids for Full Duplex Simultaneous Bidirectional Signaling Links

Yuan, Chen; Naguib, Ahmed; Shekhar, Sudip

doi:10.1109/tcsi.2019.2962359

Cited by 17 publications

(12 citation statements)

References 27 publications

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“…The interface with a large number of lanes, although has low channel losses but suffers from the issue of crosstalk between them, which further deteriorates the performance with an increase in the lane density or baud-rate [9]- [11]. Reduction in the number of lanes is possible by using simultaneous bidirectional (SBD) or full-duplex (FD) communication between the high-performance modules.…”

Section: Introductionmentioning

confidence: 99%

“…The authors are with the Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai -400076, India (email: sandeepgoyal@ee.iitb.ac.in; ganpatp@ee.iitb.ac.in; shalabh@ee.iitb.ac.in). transmitter causes a severe self-interference (SI) at the nearend receiver [11], [12]. In addition, there can be echoes of the transmitted signal at the receiver due to a mismatch between the source and load impedances, and back reflections from the channel.…”

Section: Introductionmentioning

confidence: 99%

“…They support suppression only at low baud-rates and have larger form factors, making them unattractive for high-density and high-speed interconnects. To achieve higher throughputs, recent high-speed FD interconnects use hybrids with active circuits for interference suppression [11], [12], [16]- [20]. These hybrids effectively consist of one of the following: (i) a scaled replica generator with a subtractor [17]; (ii) a comparator with dynamic referencing [18], [21], [22]; (iii) a resistive or a capacitive bridge [11], [19]; (iv) a resistor-transconductor (Rgm) cell [12], [16]; and (v) a directional inverter/buffer (DIB) with weighted cancellation paths [23].…”

Section: Introductionmentioning

confidence: 99%

“…To achieve higher throughputs, recent high-speed FD interconnects use hybrids with active circuits for interference suppression [11], [12], [16]- [20]. These hybrids effectively consist of one of the following: (i) a scaled replica generator with a subtractor [17]; (ii) a comparator with dynamic referencing [18], [21], [22]; (iii) a resistive or a capacitive bridge [11], [19]; (iv) a resistor-transconductor (Rgm) cell [12], [16]; and (v) a directional inverter/buffer (DIB) with weighted cancellation paths [23]. The main limitation in these schemes is that the AFEs do not account for the delay spread of the transmitted pulses that causes SI over multiple bit periods.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A True Full-Duplex IO (TFD-IO) with Background SI cancellation for High-Density Interfaces

Goyal¹,

Gupta²,

Parulekar³

2021

Preprint

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In this work, we have proposed and experimentally demonstrated a true full-duplex IO (TFD-IO) for high-speed high-density interfaces. The proposed TFD-IO can be used as an independent module that converts a unidirectional IO/interconnect to a fully bidirectional IO/interconnect, to ideally double the throughput of the high-speed interface. The TFD-IO uses a correlation-based technique to cancel the self-interference (SI) and echoes adaptively in the background. The signals transmitted from the near-end and the far-end can use independent baud nm CMOS technology, and demonstrated with bidirectional throughputs of up to 12.8 Gb/s.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A True Full-Duplex IO (TFD-IO) with Background SI cancellation for High-Density Interfaces

Goyal¹,

Gupta²,

Parulekar³

2021

Preprint

View full text Add to dashboard Cite

show abstract

“…To achieve higher throughputs, the high-speed FD interconnects proposed/demonstrated recently have used hybrids with active circuits for interference suppression [15]- [28]. These hybrids effectively consist of one of the following: (i) a scaled replica generator with a subtractor [11]- [13], [21], [28]; (ii) a comparator with dynamic referencing [16], [20], [23]- [27]; (iii) a resistive or a capacitive bridge [21], [22]; (iv) a resistor-transconductor (R-gm) cell [17], [19]; and (v) a directional inverter/buffer (DIB) with weighted cancellation paths [29]. The main limitation in these schemes is that they do not account for the delay spread of the transmitted pulses that causes SI over multiple bit periods.…”

mentioning

confidence: 99%

A True Full-Duplex IO (TFD-IO) With Background SI Cancellation for High-Density Interfaces

Goyal

Parulekar

Gupta

2022

IEEE Trans. VLSI Syst.

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In this work, we have proposed and experimentally demonstrated a true full-duplex IO (TFD-IO) for high-speed high-density interfaces. The proposed TFD-IO can be used as an independent module that converts a unidirectional IO/interconnect to a fully bidirectional IO/interconnect, to ideally double the throughput of the high-speed interface. The TFD-IO uses a correlation-based technique to cancel the self-interference (SI) adaptively in the background. The signals transmitted from the near-end and the far-end can use independent baud-rates and signaling schemes in a TFD-IO. A proof-of-concept design of the TFD-IO module has been fabricated in a 65 nm CMOS technology, and demonstrated with bidirectional throughputs of up to 12.8 Gb/s.

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A power‐efficient current‐integrating hybrid for full‐duplex communication over chip‐to‐chip interconnects

Govindaswamy

Pasupureddi

2022

Circuit Theory & Apps

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This work proposes a power-efficient half-rate current-integrating logic (CIL) echo cancelation hybrid circuit topology for full-duplex communication for off-chip interconnects in 65 nm CMOS. The proposed hybrid topology has a low power consumption compared to traditional current-mode hybrid circuit topology implementations, thanks to the CIL hybrid topology with sample and hold front-end. The post-layout performance of the half-rate CIL hybrid includes package parasitic has a differential received signal voltage swing of 190 mV at 10 Gb/s data rate with a timing jitter of 16 ps over a 20 cm FR4 PCB interconnect. The total power consumption of the half-rate CIL hybrid is only 2 mW, and its energy efficiency is 0.4 pJ/bit. The layout of the hybrid occupies an area of 0.0008 mm 2 .

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On the Design of Low-Power Hybrids for Full Duplex Simultaneous Bidirectional Signaling Links

Cited by 17 publications

References 27 publications

A True Full-Duplex IO (TFD-IO) with Background SI cancellation for High-Density Interfaces

A True Full-Duplex IO (TFD-IO) with Background SI cancellation for High-Density Interfaces

A True Full-Duplex IO (TFD-IO) With Background SI Cancellation for High-Density Interfaces

A power‐efficient current‐integrating hybrid for full‐duplex communication over chip‐to‐chip interconnects

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