On the architecture and performance of a hybrid image rejection receiver

Chen, Chun-Chyuan; Huang, Chia-Chi

doi:10.1109/49.926359

Cited by 26 publications

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

Error analysis on single sideband modulator

Chen

Shi

Guo

2008

Micro & Optical Tech Letters

View full text Add to dashboard Cite

mm, which can be regarded as an open stub, whereas the one at 6.65 GHz is owing to the parallel coupling between the two MMRs. It is interesting to note that both the simulated and measured return-loss curves show four distinct reflection zeros, the first (last) two of which pertain to the mode splitting due to the coupling between the two MMRs that are in /4 (/2) resonance. The presence of the reflection zeros thus enhances the transmission, leading to a relatively wide and flat passband. Also shown in Figure 6 is the measured group delay, which is less than 0.56 ns in the passband. The maximum in-band group-delay variation of 0.11 ns in conjunction with the flat insertionloss response in the passband implies the good linear characteristic of the proposed wideband BPF. Presented in Figure 7 is the photograph of the fabricated wideband BPF, which measures only 6.91 ϫ 11.71 mm 2 . CONCLUSIONA wideband BPF consisting of two MMRs has been proposed and implemented in this paper. The novel MMR was formed by combining two /4 SIRs, resulting in /4 resonance at one frequency and /2 at the other. By locating the fundamental resonant frequency of the inherent /4 SIR and that of the embedded /2 SIR in the designated passband of the proposed BPF, we have successfully realized a wideband BPF. The fabricated BPF was demonstrated to have a large passband bandwidth of 1:2.2 with an insertion loss of less than 0.86 dB and a small group-delay variation of not more than 0.11 ns in the passband.

show abstract

Error analysis on single sideband modulator

Chen

Shi

Guo

2008

Micro & Optical Tech Letters

View full text Add to dashboard Cite

show abstract

A Low-Complexity Self-Calibrating Adaptive Quadrature Receiver

Cetin

Demirsoy

Kale

et al. 2006

First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)

View full text Add to dashboard Cite

show abstract

Optimization of Arithmetic Datapaths with Finite Word-Length Operands

Gopalakrishnan

Kalla

Enescu

2007

2007 Asia and South Pacific Design Automation Conference

View full text Add to dashboard Cite

This paper presents an approach to area optimization of arithmetic datapaths that perform polynomial computations over bit-vectors with finite widths. Examples of such designs abound in DSP for audio, video and multimedia computations where the input and output bit-vector sizes are dictated by the desired precision. A bit-vector of size m represents integer values reduced modulo 2 m (%2 m ). Therefore, finite wordlength bit-vector arithmetic can be modeled as algebra over finite integer rings, where the bit-vector size dictates the ring cardinality. This paper demonstrates how the number-theoretic properties of finite integer rings can be exploited for optimization of bit-vector arithmetic. Along with an analytical model to estimate the implementation cost at RTL, two algorithms are presented to optimize bit-vector arithmetic. Experimental results, conducted within practical CAD settings, demonstrate significant area savings due to our approach.I. Introduction RTL descriptions of integer datapaths that implement polynomial arithmetic are found in many practical applications, such as in digital signal processing (DSP) for audio, video and multimedia applications [1] [2]. Such designs perform a sequence of add, mult, shift type of algebraic computations over bit-vectors; hence they are generally modeled at RTL or behavioural-level as multi-variate polynomials of finite degree [2] [3]. Initial algorithmic specifications (such as a matlab model) of such systems involve data representation using floating-point formats. However, they are often implemented with fixed-point architectures in order to optimize the area, delay and power related costs of the implementation [4]. Subsequently, the fixedpoint model can be translated into an RTL description [5] -that can be subsequently synthesized into a circuit.Algebraic techniques and tools have been used for synthesis and optimization of such systems. However, for their efficient and correct modeling, it is important to account for the effect of bit-vector size of the operands on the resulting computation. In other words, a bit-vector of size m represents integer values from 0 to 2 m -1 (or integers reduced modulo 2 m ). This implies that finite word-length (m) bit-vector arithmetic manifests itself as algebra over finite integer rings (Z2m ). Properties of such finite rings should therefore be exploited for RTL optimization of bitvector arithmetic.This paper models finite word-length bit-vector arithmetic as polynomial functions (or polyfunctions) over f : Z 2 n 1 ×

show abstract

On the architecture and performance of a hybrid image rejection receiver

Cited by 26 publications

References 21 publications

Error analysis on single sideband modulator

Error analysis on single sideband modulator

A Low-Complexity Self-Calibrating Adaptive Quadrature Receiver

Optimization of Arithmetic Datapaths with Finite Word-Length Operands

Contact Info

Product

Resources

About