On the analytical modeling of concurrency control algorithms for Software Transactional Memories: The case of Commit-Time-Locking

Sanzo, Pierangelo Di; Ciciani, Bruno; Palmieri, Roberto; Quaglia, Francesco; Romano, Paolo

doi:10.1016/j.peva.2011.05.002

Cited by 27 publications

(16 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Our work is also related to the body of literature on performance modeling of TMs, which have relied on methodologies such as analytical modeling [11,26], as well as machine learning [34]. These proposals were applied to self-tune various TM parameters, and our results clearly indicate the potentiality and importance of this line of research also in the scope of HTM.…”

Section: Related Workmentioning

confidence: 73%

“…Hence, these findings highlight the relevance of devising solutions for adaptively tuning these parameters in an automated manner. The key challenge is how to do it with minimal overhead, given that the cost imposed by self-tuning approaches targeting STMs (based on complex machine-learning [34] or analytical models [11]) is going to be strongly amplified in HTM settings because there exists no instrumentation as in STMs. In the light of these findings, we have concurrently obtained some initial results with regard to this research direction [15].…”

Section: Research Directions Suggested By Our Studymentioning

confidence: 99%

See 1 more Smart Citation

Virtues and limitations of commodity hardware transactional memory

Diegues

Romano

Rodrigues

2014

Proceedings of the 23rd International Conference on Parallel Architectures and Compilation

Self Cite

View full text Add to dashboard Cite

Over the last years Transactional Memory (TM) gained growing popularity as a simpler, attractive alternative to classic lock-based synchronization schemes. Recently, the TM landscape has been profoundly changed by the integration of Hardware TM (HTM) in Intel commodity processors, raising a number of questions on the future of TM.We seek answers to these questions by conducting the largest study on TM to date, comparing different locking techniques, hardware and software TMs, as well as different combinations of these mechanisms, from the dual perspective of performance and power consumption.Our study sheds a mix of light and shadows on currently available commodity HTM: on one hand, we identify workloads in which HTM clearly outperforms any alternative synchronization mechanism; on the other hand, we show that current HTM implementations suffer of restrictions that narrow the scope in which these can be more effective than state of the art software solutions. Thanks to the results of our study, we identify a number of compelling research problems in the areas of TM design, compilers and self-tuning.

show abstract

Section: Related Workmentioning

confidence: 73%

Section: Research Directions Suggested By Our Studymentioning

confidence: 99%

Virtues and limitations of commodity hardware transactional memory

Diegues

Romano

Rodrigues

2014

Proceedings of the 23rd International Conference on Parallel Architectures and Compilation

Self Cite

View full text Add to dashboard Cite

show abstract

“…A number of analytical models of concurrency control for database management systems have been proposed in the literature [35], [1], [37], [9]. More recently, several analytical models have been proposed for the concurrency control algorithms adopted by software implementations of TM [38], [21], [8], [14], [12], [32], [13]. The key difference with respect to these approaches is that in our model we consider peculiar characteristics of the concurrency control of HTM, including the co-existence of optimistic techniques (i.e., speculative execution of parallel transactions) and of a sequential/pessimistic fallback path.…”

Section: Related Workmentioning

confidence: 99%

An Analytical Model of Hardware Transactional Memory

Castro

Romano

Didona

et al. 2017

2017 IEEE 25th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS

Self Cite

View full text Add to dashboard Cite

Abstract-This paper investigates the problem of deriving a white box performance model of Hardware Transactional Memory (HTM) systems. The proposed model targets TSX, a popular implementation of HTM integrated in Intel processors starting with the Haswell family in 2013.An inherent difficulty with building white-box models of commercially available HTM systems is that their internals are either vaguely documented or undisclosed by their manufacturers. We tackle this challenge by designing a set of experiments that allow us to shed lights on the internal mechanisms used in TSX to manage conflicts among transactions and to track their readsets and writesets.We exploit the information inferred from this experimental study to build an analytical model of TSX focused on capturing the impact on performance of two key mechanisms: the concurrency control scheme and the management of transactional meta-data in the processor's caches. We validate the proposed model by means of an extensive experimental study encompassing a broad range of workloads executed on a real system.

show abstract

“…System maintains these versions until the limitation of memory or a success commit. Towards the former situation, Sanzo et al have considered a realistic execution model that currently used by several Software Transactional Memories (STM) systems [8]. In the latter scenario, also the traditional issue of database isolation, Bernstein et al have surveyed kinds of concurrency control schemes, and compared MVCC with them by analytical and experimental conclusions [1].…”

Section: Multi-version Concurrency Controlmentioning

confidence: 99%

“…This kind of discipline is called firstcommitter-wins rule (FCWR) in queueing theory [7]. Researchers have studied the effectiveness and performance of MVCC by taking simulation experiments [8], [9], [10]. Thus, we consider, in this paper, a stochastic model of systems with MVCC from the view of queueing analysis.…”

Section: Introductionmentioning

confidence: 99%

Modeling and Analysis of Multi-version Concurrent Control

Chen

Okamura

2013

2013 IEEE 37th Annual Computer Software and Applications Conference

View full text Add to dashboard Cite

A multi-version concurrent control (MVCC) is widely spread as an important scheme to ensure the data integrity even in on-line storage services such as Dropbox as well as database management system. The scheme of MVCC is to make a snapshot of the current data before access to the data, and to compare the snapshot with the original data just before the update is committed. This discipline is called first-committer-wins rule (FCWR). This paper focuses on the performance evaluation of MVCC based on a stochastic model. According to queueing analysis, we derive quantitative performance measures from the model analytically. Further, we reveal the effectiveness of MVCC by comparing with the serializable policy.

show abstract

On the analytical modeling of concurrency control algorithms for Software Transactional Memories: The case of Commit-Time-Locking

Cited by 27 publications

References 22 publications

Virtues and limitations of commodity hardware transactional memory

Virtues and limitations of commodity hardware transactional memory

An Analytical Model of Hardware Transactional Memory

Modeling and Analysis of Multi-version Concurrent Control

Contact Info

Product

Resources

About