Proceedings of the 23rd International Conference on Parallel Architectures and Compilation 2014
DOI: 10.1145/2628071.2628080
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Abstract: Over the last years Transactional Memory (TM) gained growing popularity as a simpler, attractive alternative to classic lock-based synchronization schemes. Recently, the TM landscape has been profoundly changed by the integration of Hardware TM (HTM) in Intel commodity processors, raising a number of questions on the future of TM.We seek answers to these questions by conducting the largest study on TM to date, comparing different locking techniques, hardware and software TMs, as well as different combinations … Show more

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Cited by 52 publications
(33 citation statements)
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References 43 publications
(44 reference statements)
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“…A recent study of applying TSX to garbage collectors demonstrates performance improvement of 1.5-2x, while achieving similar improvement with software transactional memory (STM), which suggests that hardware implementations have a lot of space for improvements [17]. Finally, a comparison study of a standard transaction memory suite as well as a number of other stress tests concludes that TSX outperforms software approaches by 3.3x for short critical sections, while both locking and STM are still better for long critical sections [2].…”
Section: Related Workmentioning
confidence: 88%
“…A recent study of applying TSX to garbage collectors demonstrates performance improvement of 1.5-2x, while achieving similar improvement with software transactional memory (STM), which suggests that hardware implementations have a lot of space for improvements [17]. Finally, a comparison study of a standard transaction memory suite as well as a number of other stress tests concludes that TSX outperforms software approaches by 3.3x for short critical sections, while both locking and STM are still better for long critical sections [2].…”
Section: Related Workmentioning
confidence: 88%
“…In this study, we select as reference TM implementation TinySTM [18], a software-based TM that has been shown to excel in a wide range of workloads [26]. TinySTM comes with different contention managers including exponential back-off with busy waiting.…”
Section: Discussionmentioning
confidence: 99%
“…Rughetti [24], [25] studied the performance and energy trade-offs of various algorithms; the study showed the necessity of adaptability within TM to minimize data contention as it is the main source of energy consumption. Diegues et al [26] evaluated the performance and energy efficiency of different TM implementations, including hardware-based (HTM), software-based (STM) and hybrid (HyTM) using a large number of popular benchmarks. The results of this study highlight that the choice of the right TM implementation is strongly workload dependant.…”
Section: Related Workmentioning
confidence: 99%
“…These overheads can be avoided by delegating the implementation of the TM abstraction to hardware mechanisms, an approach that goes under the name of hardware transactional memory (HTM). While a number of alternative HTM designs have been proposed in the literature, the HTM implementations that are currently commercially available [24], [30] are built as relatively non-intrusive extensions of the cache coherency algorithm and, as such, suffer from several restrictions [16], [20]. Overall, make the performance of HTM is much dependent on a number of workload parameters and architectural design choices [16], [20], [28], [15], [10] -which makes the problem of predicting the performance achievable by HTM-based applications a very challenging task.…”
Section: Introductionmentioning
confidence: 99%
“…The latter approach provides more flexibility, allowing for tuning not only the maximum number of hardware attempts, which we call the budget, but also how such budget should be consumed in presence of different abort types [16].…”
Section: Introductionmentioning
confidence: 99%