On synthetic benchmark generation methods

Verplaetse, P.; Campenhout, J. Van; Stroobandt, Dirk

doi:10.1109/iscas.2000.858726

Cited by 17 publications

(16 citation statements)

References 11 publications

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“…However, Verplaetse et al [2000] show that GEN does not preserve locality very well. In Hutton et al [2002], the tools are extended to include sequential circuits.…”

Section: Benchmark Circuit Generationmentioning

confidence: 93%

Perturb+mutate

Grant

Lemieux

2008

ACM Trans. Reconfigurable Technol. Syst.

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CAD tool designers are always searching for more benchmark circuits to stress their software. In this article we present a heuristic method to generate benchmark circuits specially suited for incremental place-and-route tools. The method removes part of a real circuit and replaces it with an altered version of the same circuit to mimic an incremental design change. The alteration consists of two steps: mutate followed by perturb. The perturb step exactly preserves as many circuit characteristics as possible. While perturbing, reproduction of interconnect locality, a characteristic that is difficult to measure reliably or reproduce exactly, is controlled using a new technique, ancestor depth control (ADC). Perturbing with ADC produces circuits with postrouting properties that match the best techniques known to-date. The mutate step produces targetted mutations resulting in controlled changes to specific circuit properties (while keeping other properties constant). We demonstrate one targetted mutation heuristic, scale, to significantly change circuit size with little change to other circuit characteristics. The method is simple enough for inclusion in a CAD tool directly, and fast enough for use in on-the-fly benchmark generation.

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“…However, Verplaetse et al [2000] show that GEN does not preserve locality very well. In Hutton et al [2002], the tools are extended to include sequential circuits.…”

Section: Benchmark Circuit Generationmentioning

confidence: 93%

Perturb+mutate

Grant

Lemieux

2008

ACM Trans. Reconfigurable Technol. Syst.

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“…A circuit is characterized with respect to a circuit space. A circuit space [13] is a multi-dimensional space formed by the set of characteristic parameters that include size parameters, topographical parameters, and functional parameters. A set of realistic circuits for similar applications forms a cloud in the circuit space.…”

Section: Characteristic Circuit Parameters and Empirical Lawsmentioning

confidence: 99%

“…Size parameters [13]: These include the number of gates and flip-flops/logic modules, the number of nets, and the number of primary inputs/outputs. 2.…”

Section: Circuit Parametersmentioning

confidence: 99%

Synthetic benchmark digital circuits: A survey

Srivani¹,

Kamakoti²

2012

IETE Tech Rev

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Today's VLSI CAD tools are to be designed to handle tomorrow's designs. But, what are tomorrow's designs? How large and complex will they be? are important questions, realistic answers for which are necessary for the tool architects. The scenario is similar in the case of hardware architects including those who design processors and FPGAs. For the VLSI CAD tool and FPGA architects, the synthetic benchmark circuits (SBCs) come to their rescue by providing representative designs of tomorrow. This paper elaborates on the various techniques reported in the literature for generation of SBCs. It also presents a case study of generating a SBC for accelerated life testing of an FPGA. The paper concludes posing interesting open issues in this field.

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“…The circuit level netlist generation is a computer-performed method for generating a circuit level netlist from a logic design of an application specific integrated circuit [1] .A number of approaches to benchmark netlist generation were presented in [2], [3], [4], [5], [6], and [7]. Generating random benchmark circuits for routability measurement was first done by Darnauer et al [3].…”

Section: Generation Of Benchmark Circuitsmentioning

confidence: 99%

“…Tool gnl [6] is based on a bottom-up clustering approach according to Rent's rule [8]. At last, [7] reviewed existing benchmark generation methods and discussed the advantages and drawbacks of different methods through direct validation.…”

Section: Generation Of Benchmark Circuitsmentioning

confidence: 99%

Optimization of Chip Interconnect Area by using Interconnect Length and Width

Prasad¹,

Venkatarami²

2010

IJCA

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This paper presents methodologies that provide better correlation between the apriori and posteriori estimation of interconnect length, width, area and power. A method to generate random realistic benchmark circuits for analysis is implemented. A prediction model that predicts the length, width, area and power of the benchmark circuit is developed. The net list is passed through the placement and routing phases to obtain the actual length. From the estimated length, the width, area and power are estimated. The effectiveness of the prediction technique used is validated from the results obtained. We postulate that the predicted area which comes out with a smaller error percentage than predicted length can be used as a termination condition in Simulated Annealing for placement. Results are compared for proving optimization with Lagrange's Method.

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On synthetic benchmark generation methods

Cited by 17 publications

References 11 publications

Perturb+mutate

Perturb+mutate

Synthetic benchmark digital circuits: A survey

Optimization of Chip Interconnect Area by using Interconnect Length and Width

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