2009 34th IEEE Photovoltaic Specialists Conference (PVSC) 2009
DOI: 10.1109/pvsc.2009.5411311
|View full text |Cite
|
Sign up to set email alerts
|

On space plasma ground test methodologies and related solar array design considerations

Abstract: Challenges associated with the design, testing, and qualification of space solar arrays for operation in plasma environments have led to the creation of collection of ground test and design guidelines, standards, and requirements. Discussions summarized herein examine unique design aspects affecting array performance in plasma environments and review test / analysis routines appropriate for typical space solar array production methods.

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2

Citation Types

0
2
0

Year Published

2017
2017
2017
2017

Publication Types

Select...
2

Relationship

0
2

Authors

Journals

citations
Cited by 2 publications
(2 citation statements)
references
References 12 publications
0
2
0
Order By: Relevance
“…Other important strategies are to ensure that any potential problems such as floating conductors and dielectrics have either appropriate bleed paths to reduce charge build up or filters to minimize the size and passage of any resultant ESD pulses. Finally, lab testing is sometimes carried out to investigate the susceptibility of hardware to ESD, and the impact should occur [Likar et al, 2009;Wright et al, 2012;Hoang et al, 2012;Wong et al, 2013, Likar et al, 2013.…”
Section: Design Phasementioning
confidence: 99%
“…Other important strategies are to ensure that any potential problems such as floating conductors and dielectrics have either appropriate bleed paths to reduce charge build up or filters to minimize the size and passage of any resultant ESD pulses. Finally, lab testing is sometimes carried out to investigate the susceptibility of hardware to ESD, and the impact should occur [Likar et al, 2009;Wright et al, 2012;Hoang et al, 2012;Wong et al, 2013, Likar et al, 2013.…”
Section: Design Phasementioning
confidence: 99%
“…Other important strategies are to ensure that any potential problems such as floating conductors and dielectrics have either appropriate bleed paths to reduce charge build up or filters to minimize the size and passage of any resultant ESD pulses. Finally, lab testing is sometimes carried out to investigate the susceptibility of hardware to ESD, and the impact should occur [Likar et al, 2009;Wright et al, 2012;Hoang et al, 2012;Wong et al, 2013, Likar et al, 2013. 2.2.3.…”
Section: Design Phasementioning
confidence: 99%