On RTL to TLM Abstraction to Benefit Simulation Performance and Modeling Productivity in NoC Design Exploration

Horsinka, Sven Alexander; Meyer, Rolf; Wagner, Jan; Buchty, Rainer; Berekovic, Mladen

doi:10.1145/2685342.2685349

Cited by 2 publications

(2 citation statements)

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“…With SocRocket we assembled a platform to simulate an crosssection of the EMC2-DP hardware for special heterogeneous use cases. Said platform consists of the core components of the GRLib library with the LEON3 Processor extended by an ARM Cortex-A9 [20], MicroBlaze and for interconnection a NoC simulation executing tasks of different cricitality levels [5]. The Zynq inside the EMC2-DP hardware uses an AMBA interconnect, this is replicated inside the SoCRocket simulation platform, enabling engineers to evaluate accellerator algorithms within a realistic design environment.…”

Section: Platform Noc Simulation With Emc2 Socrocketmentioning

confidence: 99%

A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project $$EMC^2$$

Isakovic

Grosu

Ratasich

et al. 2017

Lecture Notes in Computer Science

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In the sandbox world of cyber-physical systems and internetof-things a number of applications is only eclipsed by a number of products that provide solutions for specific problem or set of problems. Initiatives like the European project EM C 2 serve as cross-disciplinary incubators for novel technologies and fuse them together with state-ofthe-art industrial applications. This paper reflects on challenges in scope of hardware architectures and related technologies. It also provides a short overview of several technologies explored in the project that provide bridging solutions for these problems.

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Section: Platform Noc Simulation With Emc2 Socrocketmentioning

confidence: 99%

A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project $$EMC^2$$

Isakovic

Grosu

Ratasich

et al. 2017

Lecture Notes in Computer Science

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“…It allows to simulate the NoC 1000 times faster with more than 90% of accuracy [8], [9]. Horsinka et al [10] also proposed a TLM NoC simulator integrated in a multi-level simulation framework.…”

Section: Related Workmentioning

confidence: 99%

Speed and accuracy dilemma in NoC simulation: What about memory impact?

Selva

Gamatié

Novo

et al. 2016

2016 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)

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Network on Chip (NoC) communication infrastructures are increasingly being used in modern manycore architectures. Many industrial and research NoC simulators have been proposed in the last years in order to facilitate the design of such communication infrastructures. As any simulator, all of them have to trade off speed and accuracy. Simulation time directly depends on the simulation accuracy. It also directly depends on the complexity of the system to be simulated, e.g., the number of cores and their unit complexity. In this work, we show that the memory footprint of NoC simulators can be a serious factor limiting the simulation of manycore architectures with a large number of cores. We first quantitatively compare the memory footprint of a transactional level modeling NoC simulator and its cycle-accurate counterpart to show that memory footprint is a concern. Then, we show that memory footprint is also largely impacted by the choice of the programming abstraction by comparing two cycle-accurate simulators written using different application programming interfaces, i.e., plain C++ and SystemC.

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On RTL to TLM Abstraction to Benefit Simulation Performance and Modeling Productivity in NoC Design Exploration

Cited by 2 publications

References 10 publications

A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project $$EMC^2$$

A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project $$EMC^2$$

Speed and accuracy dilemma in NoC simulation: What about memory impact?

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