On-Resistance in the Aldmost

Nanz, G.; Dickinger, P.; Kausel, Wilfried; Selbeherr, S.

doi:10.1051/jphyscol:19884131

Cited by 5 publications

(2 citation statements)

References 3 publications

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“…This lateral DMOS transistor has been analysed previously. [14][15][16] In Figure 13 the geometry can be seen; in Figure 14 the doping profile is shown.…”

Section: Geometries and Doping Projiles Of Examplesmentioning

confidence: 99%

Self‐adaptive space and time grids in device simulation

Nanz¹,

Kausel

Selberherr³

1991

Numerical Meth Engineering

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SUMMARYFor the solution of the three basic semiconductor equations in two space dimensions fully self-adaptive grids are a powerful tool to optimize the ratio between the number of unknowns and the accuracy of the solution. For the method of finite differences hardly any mathematically founded criterion for automatic grid control can be given which can be implemented in a computer program with acceptable effort. Therefore most of the strategies for self-adaptive grid control are totally heuristic or derived from physical properties.In this paper we present criteria for the design of an initial space grid. We discuss some conventional strategies for the automatic control of space grids (e.g. equidistribution of the local discretization error) and present new criteria (e.g. degree of cohpling of the equations, physical properties like net generation rate). For the time grid an automatic step length control algorithm is presented and the interaction between space and time grid is analysed. Throughout the paper the results are illustrated by realistic examples.

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“…This lateral DMOS transistor has been analysed previously. [14][15][16] In Figure 13 the geometry can be seen; in Figure 14 the doping profile is shown.…”

Section: Geometries and Doping Projiles Of Examplesmentioning

confidence: 99%

Self‐adaptive space and time grids in device simulation

Nanz¹,

Kausel

Selberherr³

1991

Numerical Meth Engineering

Self Cite

View full text Add to dashboard Cite

show abstract

“…A major drawback of lateral devices is their high on-resistance. To improve the on-resistance of such devices two technics have been proposed : using a semiresistive (such as SIPOS) layer between the channel and drain metallizations [2], or implanting a shallow lightly doped layer at the surface of the wafer [3].…”

Section: Off Statementioning

confidence: 99%