On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits

Keller, Kai; Takahashi, Hiroshi; Saluja, Kewal K.; Takamatsu, Yasushi

doi:10.1109/test.2001.966675

Cited by 17 publications

(7 citation statements)

References 10 publications

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“…However, testing for crosstalk-induced effects on delays has recently received more attention [3][4][5][6][7][8][9][10][11]. Since the pattern generation for crosstalk-induced delay faults requires timing information into the automatic test pattern generation process, reducing high complexity of the ATPG process is major issue of previous test generation method for crosstalk-induced delay faults.…”

Section: Introductionmentioning

confidence: 99%

XPDF-ATPG: An Efficient Test Pattern Generation for Crosstalk-Induced Faults

Chun

Kim

et al. 2008

2008 17th Asian Test Symposium

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In this paper, we propose a new test generation method for delay faults considering crosstalk-induced delay effects, based on a conventional delay ATPG technique in order to reduce the complexity of previous ATPG algorithm for crosstalk delay faults and to consider multiple aggressor crosstalk faults to maximize the noise of the victim line. Since the proposed ATPG for crosstalk-induced delay faults uses the physical and timing information, the proposed ATPG can reduce the search space of the backward implication of the aggressor's constraints and it is helpful for reducing the time cost of the ATPG than previous works. In addition, since the proposed technique targets on the critical path for the original delay test as the victim lines, it can improve test effectiveness of delay testing. Experimental results demonstrate the effectiveness of the proposed method.

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Section: Introductionmentioning

confidence: 99%

XPDF-ATPG: An Efficient Test Pattern Generation for Crosstalk-Induced Faults

Chun

Kim

et al. 2008

2008 17th Asian Test Symposium

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“…For example, in the ISCAS'89 benchmark circuit s38584, the total number of aggressor and victim line pairs is over 400 million. It is clearly important to identify crosstalk-induced transition faults that need to be tested, because certain transition faults may not cause faulty behavior in sequential circuits [9]. Kirkpatrick and his co-authors [7], [8] have proposed using layout information from the physical design to obtain the target crosstalk-fault list and derive tests for these faults only.…”

Section: Introductionmentioning

confidence: 99%

“…Similarly, we use the potential correlation between logic design and physical layout to deduce a target fault list for crosstalk faults [12]. However, we believe that our paper [9] is the first research paper in this area that addresses the issue of fault-list reduction of crosstalk-induced transition faults in synchronous sequential circuits. In our method, we identify signal-pairs that should be included in the target crosstalk fault list, and also identify classes of false crosstalk faults that cannot be tested and/or need not be tested.…”

Section: Introductionmentioning

confidence: 99%

“…In our method, we identify signal-pairs that should be included in the target crosstalk fault list, and also identify classes of false crosstalk faults that cannot be tested and/or need not be tested. This paper is an expansion of the work presented in [9], and it contains fewer constraints and more experimental results. Two other methods [10], [11] have been proposed following our work presented at the 2001 International Test Conference [9].…”

Section: Introductionmentioning

confidence: 99%

“…This paper is an expansion of the work presented in [9], and it contains fewer constraints and more experimental results. Two other methods [10], [11] have been proposed following our work presented at the 2001 International Test Conference [9]. In [10], a crosstalk target identification framework was proposed that is composed of a set of extractors and filters which together identify the target faults.…”

Section: Introductionmentioning

confidence: 99%

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A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits

Takahashi

Keller

et al. 2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, we describe a method of identifying a set of target crosstalk faults which may need to be tested in synchronous sequential circuits. Our method classifies the pairs of aggressor and victim lines, using topological and timing information, to deduce a set of target crosstalk faults. In this process, our method also identifies the false crosstalk faults that need not (and/or cannot) be tested in synchronous sequential circuits. Experimental results for ISCAS'89 and ITC'99 benchmark circuits show that the proposed method is CPU time efficient in obtaining the reduced lists of the target crosstalk faults. Also, the lists of the target crosstalk faults obtained by our method are substantially smaller than the sets of all possible combinations of faults.Index Terms-Crosstalk faults, lists of the target crosstalk faults, synchronous sequential circuits.

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Selection of Crosstalk-Induced Faults in Enhanced Delay Test

2005

J Electron Test

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On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits

Cited by 17 publications

References 10 publications

XPDF-ATPG: An Efficient Test Pattern Generation for Crosstalk-Induced Faults

XPDF-ATPG: An Efficient Test Pattern Generation for Crosstalk-Induced Faults

A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits

Selection of Crosstalk-Induced Faults in Enhanced Delay Test

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