On Parallel Searching

Abstract

We investigate the complexity of searching a sorted table of n elements on a synchronous, shared memory parallel computer with p processors. We show that f(lg n-lgp) steps are required if concurrent accesses to the same memory cell are not allowed, whereas O(lg n/lg p) steps are sufficient if simultaneous reads are allowed. The lower bound is valid even if only communication steps are counted, and the computational power of each processor is not restricted. In this model, (R)(x/-g n) steps are required for searching when the number of processors is unbounded. If the amount of information that a memory cell may store is restricted, then the time complexity for searching with an unbounded number of processors is O(lg n/lg lg n). If the amount of information a processor may hold is also restricted, then an fl(lg n) lower bound holds. These lower bounds are first proven for comparison-based algorithms; it is next shown that comparison-based algorithms are as powerful as more general ones in solving problems defined in terms of the relative order of the inputs.

Complexity of Boolean functions on PRAMs - Lower bound techniques

“…Snir [22] defines a range searching problem of size n: For an input consisting of n + 1 numbers x 1 , . .…”

“…< x n , find the index i such that x i < y ≤ x i+1 (by definition, x 0 = −∞ and x n+1 = ∞). There is an algorithm that solves the range searching problem of size n in O( √ log n) time [22]. Snir shows a matching lower bound:…”

Parallelism Always Helps

“…A PRAM may allow concurrent-read and concurrent-write (CRCW) operations, concurrent-read and exclusive-write (CREW) operations, or exclusive-read and exclusive-write (EREW) operations [1,22,25]. In a CRCW PRAM, some mechanism is necessary to resolve the simultaneous write conflicts [1,7,21].…”

Limits on the power of concurrent-write parallel machines

“…Snir (1985), for example, has given a formal explanation of the actions of a most powerful EREW PRAM which is essentially a method of describing the ways that the processor and cell partitions of that machine may be combined during a computation.…”