On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs

Taouil, Mottaqiallah; Hamdioui, Said; Verbree, Jouke; Marinissen, Erik Jan

doi:10.1109/test.2010.5699218

Cited by 33 publications

(41 citation statements)

References 15 publications

(26 reference statements)

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“…Wafer matching has been researched to mitigate this drawback by many authors [17,20,21,24,27]; it is a technique based on the matching of wafers with similar fault maps. In case of a large stack size or low die yield, the improvement can be significant.…”

Section: W2w Matchingmentioning

confidence: 99%

“…The improvement decreases for higher die yield. For example, for a stack size of two layers with a die yield of 85 % and 1,278 dies per wafer, wafer matching is able to increase the compound yield from 72.3 % (for random W2W stacking) to 73.1 % [24].…”

Section: W2w Matchingmentioning

confidence: 99%

“…Improve yield for 3D circuits based on wafer matching has been discussed by many authors [17,20,21,24,27]. In this paper, we use the adaptive Best Pair (BP) algorithm [24] to determine the yield increase due to wafer matching.…”

Section: Yield and Cost Models For Wafer Matchingmentioning

confidence: 99%

“…In this paper, we use the adaptive Best Pair (BP) algorithm [24] to determine the yield increase due to wafer matching.…”

Section: Yield and Cost Models For Wafer Matchingmentioning

confidence: 99%

“…In addition, it compares the results with wafer matching [24]; a technique to improve W2W stacking by matching wafers with similar fault distributions. Finally, it combines both techniques and investigates the realized yield improvement.…”

Section: Introductionmentioning

confidence: 99%

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Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

Taouil

Hamdioui

2012

J Electron Test

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Recent enhancements in process development enable the fabrication of three dimensional stacked ICs (3D-SICs) such as memories based on Wafer-to-Wafer (W2W) stacking. One of the major challenges facing W2W stacking is the low compound yield. This paper investigates compound yield improvement for W2W stacked memories using layer redundancy and compares it to wafer matching. First, an analytical model is provided to prove the added value of layer redundancy. Second, the impact of such a scheme on the manufacturing cost is evaluated. Third, these two parts are integrated to analyze the tradeoff between yield improvement and its associated cost; the realized yield improvement is also compared to yield gain obtained when using wafer matching. The simulation results show that for higher stack sizes layer redundancy realizes a significant yield improvement as compared to wafer matching, even at lower cost. For example, for a stack size of six stacked layers and a die yield of 85 %, a relative yield improvement of 118.79 % is obtained with two redundant layers, while this is 14.03 % only with wafer matching. The additional cost due to redundancy pays off; the cost of producing a good 3D stacked memory chip reduces with 37.68 % when using layer redundancy and only with 12.48 % when using wafer matching. Moreover, the results show that the benefits of layer redundancy become extremely significant for lower die yields. Finally, layer redundancy and wafer matching are integrated to obtain further cost reductions.

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