A Novel Wafer Manipulation Method for Yield Improvement and Cost Reduction of 3D Wafer-on-Wafer Stacked ICs

Zhang, Bei; Agrawal, Vishwani D.

doi:10.1007/s10836-013-5429-1

Cited by 3 publications

(1 citation statement)

References 26 publications

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“…It is also necessary in providing known good die (KGD) information for dieto-die or die-to-wafer fabrication process. Even for waferon-wafer stacking, pre-bond TSV test helps in better wafer matching and thus improves the yield [14], [17], [20], [21]. Post-bond TSV test targets the defects that arise during the assembly process.…”

Section: Introductionmentioning

confidence: 99%

Diagnostic Tests for Pre-bond TSV Defects

Zhang

Agrawal

2015

2015 28th International Conference on VLSI Design

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Pre-bond testing and defect identification of through silicon via (TSV) is extremely important for yield assurance of 3D stacked devices. Based on a recently published pre-bond TSV probing technique, this paper proposes an ILP (integer linear programming) model to generate near-optimal set of sessions for pre-bond TSV test. The sessions generated by our model identify defective TSVs in a TSV network with the same capability as that of other available heuristic methods, but with consistently reduced test time. The ILP model is shown to reduce the pre-bond TSV test time by 38.2% for pinpointing up to two faulty TSVs in an 11-TSV network. Reducing prebond TSV test time helps reduce the manufacturing cost of 3D stacked devices. This ILP model has low complexity and an example demonstration using a commercial solver takes less than 40 seconds.

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