On-line testing of bundled-data asynchronous handshake protocols

Zeidler, Steffen; Bystrov, A.; Krstica, Milos; Kraemer, Rolf

doi:10.1109/iolts.2010.5560190

Cited by 5 publications

(2 citation statements)

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“…Even though it is basically easy to determine the presence of a fault using an external timer scheme, it might be impossible to infer its location. For this reason, special handshake checkers have been proposed to increase the testability of the handshake logic [4], [10]. These protocol checkers observe the handshake signals during normal operation in order to detect faults violating the handshake protocol.…”

Section: A Self-checking Capabilities Of Asynchronous Circuitsmentioning

confidence: 99%

A survey about testing asynchronous circuits

Zeidler

Krstić

2015

2015 European Conference on Circuit Theory and Design (ECCTD)

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Even though the asynchronous design methodology is considered to be a promising solution to upcoming challenges of designing complex integrated circuits (ICs), it is not widely accepted by the industry. Besides the lack of mature design tools, a further key inhibitor of using this design style is the widespread assumption that asynchronous circuits are difficult to test due to problems with system timing during test, nondeterminism, and difficulties with applying standard test approaches such as scan. However, there is a huge variety of approaches to handle these testing issues. This paper summarizes the different available test methodologies for asynchronous and globallyasynchronous locally-synchronous (GALS) designs and addresses their strengths and weaknesses. Moreover, it gives an overview of a methodology for testing based on the use of specific test processor, developed by IHP.

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Section: A Self-checking Capabilities Of Asynchronous Circuitsmentioning

confidence: 99%

A survey about testing asynchronous circuits

Zeidler

Krstić

2015

2015 European Conference on Circuit Theory and Design (ECCTD)

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“…A further standard technique is the adaption and integration of Built-In Self-Test (BIST) into asynchronous designs as, e.g., addressed in [8]- [10]. Furthermore, on-line test techniques have been applied, e.g., to check the correct operation of asynchronous protocols [11], [12].…”

Section: Introductionmentioning

confidence: 99%

Design of a Test Processor for Asynchronous Chip Test

Zeidler

Wolf

Krstić

et al. 2011

2011 Asian Test Symposium

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Due to asynchronous timing and arbitration asynchronous designs may behave nondeterministically. For the test of such systems, this means that an exact timing, i.e. a tester cycle, of a test response cannot be guaranteed. This behavior makes functional tests of asynchronous designs relatively complex or even impossible. Therefore, this paper presents a concept for structurally and functionally test asynchronous designs using a test processor infrastructure. To this end, we propose a low-cost 16-bit microprocessor solution with special support of asynchronous handshake signalling that can either be integrated into the device-under-test (DUT), mounted on the load board of the tester or a combination of both.

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