2018
DOI: 10.1016/j.microrel.2018.07.128
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On-line solder layer degradation measurement for SiC-MOSFET modules under accelerated power cycling condition

Abstract: In order to distinguish die-attach solder layer and bond wire degradation during power cycling tests, a simultaneous on-line measurement method is proposed in this paper. To measure accurately solder layer voltage drop, the intrinsic diode is used as heating source in place of the MOSFET switch. In this way, the measurement method becomes intrinsically insensitive to possible threshold voltage shifts, typical of accelerated test of SiC power MOSFETs. Finally, the experimental results are presented to verify th… Show more

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Cited by 21 publications
(7 citation statements)
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“…According to the accelerated lifetime testing (ALT) of the SiC power modules, as mentioned in [10]- [15], due to the CTE mismatch between the adjacent layers, the bond wire and die attach-solder layer is identified as the most vulnerable area. Moreover, the thermo-mechanical stresses coming from temperature swings in these two areas accelerate the degradation, leading to various wear-out damages such as bond wire hill-crack, bond wire lift-off and solder joint damage.…”
Section: A the Necessity To Investigate Sic Power Module's Failuresmentioning
confidence: 99%
See 1 more Smart Citation
“…According to the accelerated lifetime testing (ALT) of the SiC power modules, as mentioned in [10]- [15], due to the CTE mismatch between the adjacent layers, the bond wire and die attach-solder layer is identified as the most vulnerable area. Moreover, the thermo-mechanical stresses coming from temperature swings in these two areas accelerate the degradation, leading to various wear-out damages such as bond wire hill-crack, bond wire lift-off and solder joint damage.…”
Section: A the Necessity To Investigate Sic Power Module's Failuresmentioning
confidence: 99%
“…The total losses in the IBC comprise of MOSFET losses (switching losses, conduction losses and reverse recovery losses), inductor losses (core loss, air-gap loss and conduction loss) and ESR losses of the DC-link capacitor. The calculation of inductor and capacitor losses is derived in equations ( 11)- (15). The core geometry of the inductor is taken from the datasheet [56].…”
Section: F Detailed Electro-thermal Modelling and Validation Of The Ibc At Full Load Conditionmentioning
confidence: 99%
“…As for solder layer failure, the junction-to-case thermal resistance (or thermal impedance) is usually utilized as an indicator to indicate the solder fatigue in IGBT and SiC MOSFET [48,49]. Additionally, the solder layer resistance and junction temperature are utilized to indicate the solder layer fatigue in SiC MOSFET [50] and IGBT [51,52], respectively. The typical failure indicators of IGBT and SiC MOSFET are summarized in Table 1.…”
Section: Failure Mechanism and Indicatorsmentioning
confidence: 99%
“…Package technologies of commercial SiC MOSFET products mainly follow silicon‐based devices’ design. Similar to silicon IGBT modules, the hierarchical structure of SiC MOSFET modules consist of several layers with a different CTE [74]. Owing to the coefficient mismatch between adjacent layers and internal temperature gradients, power modules can be subjected to cyclic thermal stress, leading to fatigue damage of the die attach‐solder layer and bond wire [75].…”
Section: Reliability Of Sic Mosfetsmentioning
confidence: 99%