On improving test quality of scan-based BIST

Tsai, Huan-Chih; Cheng, Kwang-Ting; Bhawmik, Sudipta

doi:10.1109/43.856978

Cited by 25 publications

(2 citation statements)

References 16 publications

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“…Further development in the test vector set of DMST with pseudo-random numbers reduces the test’s deterministic pattern. It enables a lower number of flip-flops while improving the detection quality [ 54 ]. The compression technique was also introduced to lower the area of the required sub-circuit [ 55 , 56 ].…”

Section: Aes Dmst and Process Variationmentioning

confidence: 99%

A dual mode self-test for a stand alone AES core

et al. 2021

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Advanced Encryption Standard (AES) is the most secured ciphertext algorithm that is unbreakable in a software platform’s reasonable time. AES has been proved to be the most robust symmetric encryption algorithm declared by the USA Government. Its hardware implementation offers much higher speed and physical security than that of its software implementation. The testability and hardware Trojans are two significant concerns that make the AES chip complex and vulnerable. The problem of testability in the complex AES chip is not addressed yet, and also, the hardware Trojan insertion into the chip may be a significant security threat by leaking information to the intruder. The proposed method is a dual-mode self-test architecture that can detect the hardware Trojans at the manufacturing test and perform an online parametric test to identify parametric chip defects. This work contributes to partitioning the AES circuit into small blocks and comparing adjacent blocks to ensure self-referencing. The detection accuracy is sharpened by a comparative power ratio threshold, determined by process variations and the accuracy of the built-in current sensors. This architecture can reduce the delay, power consumption, and area overhead compared to other works.

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Section: Aes Dmst and Process Variationmentioning

confidence: 99%

A dual mode self-test for a stand alone AES core

et al. 2021

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“…Additionally, the TPG allows the automatic selection of weighted parameters to achieve its low power. The weighted pseudorandom TPG methods [10], [11] and their implementation in [12], [13] can effectively reduce the switching transitions. However, the methods [10], [11], included additional XOR transitions between the shift registers, it consumed more power and area.…”

Section: Introductionmentioning

confidence: 99%

A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture

2021

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A test pattern generator generates a pseudorandom test pattern that can be weighted to reduce the fault coverage in a built-in self-test. The objective of this paper is to propose a new weighted TPG for a scan-based BIST architecture. The motivation of this work is to generate efficient weighted patterns for enabling scan chains with reduced power consumption and area. Additionally, the pseudo-primary seed of TPG is maximized to obtain a considerable length in the weighted pseudorandom patterns. The maximum-length weighted patterns are executed by assigning separate weights to the specific scan chains using a weight-enabled clock. This approach reduces the hardware overhead and achieves a low power consumption of 26.7 nW. Moreover, the proposed weighted TPG is applied in two different test-per-scan BIST architectures and achieves accurate results. The weighted patterns are also generated with fewer switching transitions and higher fault coverages of 98.81% and 97.35% in two different BIST architectures. This process is observed with six other circuits under test as their scan chains. The simulation results are tested with a SilTerra 0.13 µm process on the Mentor Graphics IC design platform. Furthermore, the proposed weighted TPG is enlarged to a higher bit TPG, which is compared to accomplish the performance strategies. The experimental results of the proposed TPG design are compared and tabulated with existing potential TPG designs. INDEX TERMS built-in self-test (BIST), circuit under test (CUT), test-pattern generator (TPG).

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Scan BIST with biased scan test signals

Xiang

Chen

Sun

2008

Sci. China Ser. F-Inf. Sci.

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The conventional test-per-scan built-in self-test (BIST) scheme needs a number of shift cycles followed by one capture cycle. Fault effects received by the scan flipflops are shifted out while shifting in the next test vector like scan testing. Unlike deterministic testing, it is unnecessary to apply a complete test vector to the scan chains. A new scan-based BIST scheme is proposed by properly controlling the test signals of the scan chains. Different biased random values are assigned to the test signals of scan flip-flops in separate scan chains. Capture cycles can be inserted at any clock cycle if necessary. A new testability estimation procedure according to the proposed testing scheme is presented. A greedy procedure is proposed to select a weight for each scan chain. Experimental results show that the proposed method can improve test effectiveness of scan-based BIST greatly, and most circuits can obtain complete fault coverage or very close to complete fault coverage. random testability, scan-based BIST, test signal, biased random testing

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On improving test quality of scan-based BIST

Cited by 25 publications

References 16 publications

A dual mode self-test for a stand alone AES core

A dual mode self-test for a stand alone AES core

A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture

Scan BIST with biased scan test signals

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