A dual mode self-test for a stand alone AES core

Hossain, Md. Farhad; Sakib, Taiyeb Hasan; Ashar, Muhammad; Ferdian, Rian

doi:10.1371/journal.pone.0261431

Cited by 5 publications

(4 citation statements)

References 70 publications

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“…This is because in testing using the partial-scan method, the number of flip flops that are converted into scannable flip flops is only partial or incomplete. To find out which flip flop will be used as a scannable flip flop, we can analyze the circuit with several approaches, in this case we use FSM based [19]. We proposed custom approach with the largest number of inputs and outputs of selected flip flops to achieve high result of fault coverage and test coverage as in Figure 8., Table 1 and Table 2.…”

Section: Circuit Testing With the Partial-scan Methodsmentioning

confidence: 99%

Fault Coverage Testing on the ISCAS’89 S1423 Sequential Circuit using Scan Based Design and Synopsis Tetramax

Suteddy,

Adiwilaga,

Atmanto

2022

COELITE

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We tested the ISCAS'89 S1423 series with a scan design method, both non-scan, full-scan, and partial-scan, but for the partial-scan, the method we propose uses a structured random approach. The purpose of this study is to determine the evaluation and performance with the best computational time with the proposed method to produce high fault coverage results. Testing the ISCAS'89 S1423 circuit in the form of verilog was carried out using tetramax synopsis, the partial-scan test requires a strategy in determining the flip flop to be used as a scannable flip flop, the test results using the full scan method produce 100% test coverage and fault coverage, but this method provides gate overhead loss of 24.06% and slower chip performance. To reduce the gate overhead loss, a partial-scan method will be applied with the approach of choosing from 74 DFF which will be used as scannable flip flops, the test with the best results we did through the 37 DFF approach with the highest input obtained test coverage of 98.17% and fault coverage 96.76% with 171.11 CPU Time with gate overhead reduced by 12.03%. The next approach with the best results with the approach of 50 DFF highest output plus DFF which is not self-loop obtained test coverage of 99.24% and fault coverage of 98.47% with gate overhead successfully reduced by 16.26% with CPU Time 43.39.

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Section: Circuit Testing With the Partial-scan Methodsmentioning

confidence: 99%

Fault Coverage Testing on the ISCAS’89 S1423 Sequential Circuit using Scan Based Design and Synopsis Tetramax

Suteddy,

Adiwilaga,

Atmanto

2022

COELITE

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“…Hossain et al. [ 35 ] proposed a safety model to avoid IP theft from microfluidic biochips at various stages of the biochip design process for drive sequences. Moreover, the joint extension of split manufacturing and camouflaging techniques to 3D integration in [ 52 ] is an important step forward in the prevention of hardware Trojans.…”

Section: Related Workmentioning

confidence: 99%

“…The security problem of hardware Trojans can be broadly divided into three parts: detection, localization, and failure, where the detection method of hardware Trojans has achieved excellent results by many research teams worldwide. For example, the use of a dual-mode self-test architecture approach for detecting hardware Trojans in design, manufacturing, and testing is mentioned in [35]. Sabri et al [36] proposed an SAT-Based integrated hardware Trojan detection and a localization approach through path-delay analysis.…”

Section: Related Workmentioning

confidence: 99%

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A Cost-Driven Method for Deep-Learning-Based Hardware Trojan Detection

Dong,

Yao,

et al. 2023

Sensors

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The Cyber-Physical System and even the Metaverse will become the second space in which human beings live. While bringing convenience to human beings, it also brings many security threats. These threats may come from software or hardware. There has been a lot of research on managing malware, and there are many mature commercial products, such as antivirus software, firewalls, etc. In stark contrast, the research community on governing malicious hardware is still in its infancy. Chips are the core component of hardware, and hardware Trojans are the primary and complex security issue faced by chips. Detection of hardware Trojans is the first step for dealing with malicious circuits. Due to the limitation of the golden chip and the computational consumption, the existing traditional detection methods are not applicable to very large-scale integration. The performances of traditional machine-learning-based methods depend on the accuracy of the multi-feature representation, and most of the methods may lead to instability because of the difficulty of extracting features manually. In this paper, employing deep learning, a multiscale detection model for automatic feature extraction is proposed. The model is called MHTtext and provides two strategies to balance the accuracy and computational consumption. After selecting a strategy according to the actual situations and requirements, the MHTtext generates the corresponding path sentences from the netlist and employs TextCNN for identification. Further, it can also obtain non-repeated hardware Trojan component information to improve its stability performance. Moreover, a new evaluation metric is established to intuitively measure the model’s effectiveness and balance: the stabilization efficiency index (SEI). In the experimental results for the benchmark netlists, the average accuracy (ACC) in the TextCNN of the global strategy is as high as 99.26%, and one of its stabilization efficiency index values ranks first with a score of 71.21 in all comparison classifiers. The local strategy also achieved an excellent effect, according to the SEI. The results show that the proposed MHTtext model has high stability, flexibility, and accuracy, in general.

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