On identifying and optimizing instruction sequences for dynamic compilation

Bispo, João; Cardoso, João M. P.

doi:10.1109/fpt.2010.5681454

Cited by 12 publications

(24 citation statements)

References 6 publications

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“…Previous work [7] shows that for many benchmarks, Megablocks can have coverage similar or greater than other runtime detection methods, such as monitoring short backward branches (the approach used by Warp [10]). …”

Section: Megablocksmentioning

confidence: 99%

“…For instance, Figure 1 shows a pattern of size 6 (0x174, 0x178, 0x17C, 0x180, 0x184, and 0x188). In [7], it is shown how the detection of Megablocks can be done in an efficient way.…”

Section: Megablocksmentioning

confidence: 99%

“…e architecture of the RPU was heavily in�uenced by the kind of repetitive patterns we are mapping, the Megablocks [7]. A Megablock is a pattern of instructions in the execution trace of a program and is extracted from execution instruction traces.…”

Section: Megablocksmentioning

confidence: 99%

“…e Megablock concept [7] was proposed in the context of dynamic partitioning, that is, deciding at runtime which instruction sequences executing on an GPP should be moved to dedicated hardware. We consider four steps for dynamic partitioning: detection, translation, identi�cation, and migration.…”

Section: Megablocksmentioning

confidence: 99%

“…We focus on a special kind of trace-based loop, named Megablock [7], and transform Megablocks into graph representations which are then used to generate Megablock-tailored RPUs. Megablocks are repeating patterns of elementary units of the trace (e.g., basic blocks) in the instruction stream of the program being executed.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units

Bispo

Paulino

Cardoso

et al. 2013

International Journal of Reconfigurable Computing

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e ability to map instructions running in a microprocessor to a recon�gurable processing unit (RPU), acting as a coprocessor, enables the runtime acceleration of applications and ensures code and possibly performance portability. In this work, we focus on the mapping of loop-based instruction traces (called Megablocks) to RPUs. e proposed approach considers offline partitioning and mapping stages without ignoring their future runtime applicability. We present a toolchain that automatically extracts speci�c trace-based loops, called Megablocks, from MicroBlaze instruction traces and generates an RPU for executing those loops. Our hardware infrastructure is able to move loop execution from the microprocessor to the RPU transparently, at runtime, and without changing the executable binaries. e toolchain and the system are fully operational. ree FPGA implementations of the system, differing in the hardware interfaces used, were tested and evaluated with a set of 15 application kernels. Speedups ranging from 1.26× to 3.69× were achieved for the best alternative using a MicroBlaze processor with local memory.

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Section: Megablocksmentioning

confidence: 99%

“…For instance, Figure 1 shows a pattern of size 6 (0x174, 0x178, 0x17C, 0x180, 0x184, and 0x188). In [7], it is shown how the detection of Megablocks can be done in an efficient way.…”

Section: Megablocksmentioning

confidence: 99%

Section: Megablocksmentioning

confidence: 99%

Section: Megablocksmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units

Bispo

Paulino

Cardoso

et al. 2013

International Journal of Reconfigurable Computing

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Architecture for Transparent Binary Acceleration of Loops with Memory Accesses

Paulino

Ferreira

Cardoso

2013

Lecture Notes in Computer Science

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This paper presents an extension to a hardware/software system architecture in which repetitive instruction traces, called Megablocks, are accelerated by a Reconfigurable Processing Unit (RPU). This scheme is supported by a custom toolchain able to automatically generate a RPU tailored for the execution of one or more Megablocks detected offline. Switching between hardware and software execution is done transparently, without modifications to source code or executable binaries. Our approach has been evaluated using an architecture with a MicroBlaze General Purpose Processor (GPP) softcore. By using a memory sharing mechanism, the RPU can access the GPP's data memory, allowing the acceleration of Megablocks with load/store operations. For a set of 21 embedded benchmarks, an average speedup of 1.43× is achieved, and a potential speedup of 2.09× is predicted for an implementation using a low overhead interface for communication between GPP and RPU.

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