Architecture for Transparent Binary Acceleration of Loops with Memory Accesses

Paulino, Nuno; Ferreira, Joao Canas; Cardoso, João M. P.

doi:10.1007/978-3-642-36812-7_12

Cited by 3 publications

(3 citation statements)

References 9 publications

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“…The current version of the VHDL generation tool does not deal with Megablocks with memory operations. Note that non-pipelined Megablocks have been already tested and evaluated using an FPGA board (see [14]), and there is recent work focused on adding support to memory operations [16].…”

Section: Resultsmentioning

confidence: 99%

Hardware Pipelining of Repetitive Patterns in Processor Instruction Traces

Bispo¹,

Cardoso²,

Monteiro³

2020

JICS

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Dynamic partitioning is a promising technique where computations are transparently moved from a Gene- ral Purpose Processor (GPP) to a coprocessor during application execution. To be effective, the mapping of computations to the coprocessor needs to consider aggressive optimizations. One of the mapping opti- mizations is loop pipelining, a technique extensively studied and known to allow substantial performance improvements. This paper describes a technique for pipelining Megablocks, a type of runtime loop deve- loped for dynamic partitioning. The technique transforms the body of Mega-blocks into an acyclic dataflow graph which can be fully pipe-lined and is based on the atomic execution of loop iterations. For a set of 9 ben- chmarks without memory operations, we generated pipelined hardware versions of the loops and esti-mate that the presented loop pipelining technique increases the average speedup of non-pipelined coprocessor accelerated designs from 1.6× to 2.2×. For a larger set of 61 benchmarks which include memory operations, we estimate through simulation a speedup increase from 2.5× to 5.6× with this technique.

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Section: Resultsmentioning

confidence: 99%

Hardware Pipelining of Repetitive Patterns in Processor Instruction Traces

Bispo¹,

Cardoso²,

Monteiro³

2020

JICS

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“…This work focuses on the third point, transparent control flow transfer in the context of HPC platforms-specifically, the Xeon + FPGA platform [9]. Several proposals have been made for a mechanism capable of transparently transferring control flow between a CPU and an accelerator, but most of them target embedded platforms [10][11][12]. Embedded platforms benefit from a heterogeneous computational model, but allow much more fine-grained control, leading to approaches that are not directly transferable to HPC.…”

mentioning

confidence: 99%

“…An input trigger is then sent to the BERET co-processor along with some configuration data. Another approach is proposed in [12], where a local memory bus injector is responsible for triggering the transfer of the control flow. This block watches the instruction bus, and when it detects the start of a hotspot, it modifies the instruction flow to invoke a subroutine that takes over the transfer.…”

mentioning

confidence: 99%

Transparent Control Flow Transfer between CPU and Accelerators for HPC

Granhão

Ferreira

2021

Electronics

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Heterogeneous platforms with FPGAs have started to be employed in the High-Performance Computing (HPC) field to improve performance and overall efficiency. These platforms allow the use of specialized hardware to accelerate software applications, but require the software to be adapted in what can be a prolonged and complex process. The main goal of this work is to describe and evaluate mechanisms that can transparently transfer the control flow between CPU and FPGA within the scope of HPC. Combining such a mechanism with transparent software profiling and accelerator configuration could lead to an automatic way of accelerating regular applications. In this work, a mechanism based on the ptrace system call is proposed, and its performance on the Intel Xeon+FPGA platform is evaluated. The feasibility of the proposed approach is demonstrated by a working prototype that performs the transparent control flow transfer of any function call to a matching hardware accelerator. This approach is more general than shared library interposition at the cost of a small time overhead in each accelerator use (about 1.3ms in the prototype implementation).

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A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses

Paulino

Ferreira

Cardoso

2014

ACM Trans. Reconfigurable Technol. Syst.

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This article presents a reconfigurable hardware/software architecture for binary acceleration of embedded applications. A Reconfigurable Processing Unit (RPU) is used as a coprocessor of the General Purpose Processor (GPP) to accelerate the execution of repetitive instruction sequences called Megablocks. A toolchain detects Megablocks from instruction traces and generates customized RPU implementations. The implementation of Megablocks with memory accesses uses a memory-sharing mechanism to support concurrent accesses to the entire address space of the GPP's data memory. The scheduling of load/store operations and memory access handling have been optimized to minimize the latency introduced by memory accesses. The system is able to dynamically switch the execution between the GPP and the RPU when executing the original binaries of the input application. Our proof-of-concept prototype achieved geometric mean speedups of 1.60× and 1.18× for, respectively, a set of 37 benchmarks and a subset considering the 9 most complex benchmarks. With respect to a previous version of our approach, we achieved geometric mean speedup improvements from 1.22 to 1.53 for the 10 benchmarks previously used.

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Architecture for Transparent Binary Acceleration of Loops with Memory Accesses

Cited by 3 publications

References 9 publications

Hardware Pipelining of Repetitive Patterns in Processor Instruction Traces

Hardware Pipelining of Repetitive Patterns in Processor Instruction Traces

Transparent Control Flow Transfer between CPU and Accelerators for HPC

A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses

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