On design and implementation of a decimation filter for multistandard wireless transceivers

Ghazel, Adel; Naviner, Lírida Alves de Barros; Grati, Khaled

doi:10.1109/twc.2002.805093

Cited by 28 publications

(8 citation statements)

References 14 publications

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“…As a consequence, the general expression of the static power consumption for a direct form FIR filter (Figure 2) in the 90 nm technology could be written as shown in (9).…”

Section: Static Power Consumption Model Thementioning

confidence: 99%

Power Consumption Models for Decimation FIR Filters in Multistandard Receivers

et al. 2012

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Decimation filters are widely used in communication-embedded systems. In fact, decimation filters are useful for implementing channel filtering or selection with low-computation complexity requirements. Many multistandard receiver designs that are required in ubiquitous embedded systems are based on a cascade of decimation filter processing. Filter number and implementation architectures have a significant impact on system performances, such as computation complexity, area, throughput, and power consumption. In this work, we present filter power consumption estimation models for FIR filters. Power consumption models were obtained from a large number of FIR filter syntheses using a direct form. Several curves that estimate power consumption were extracted from these synthesis results. Then, we have evaluated the impact of polyphase decomposition on power consumption of FIR filter and compared it with the direct form results. Some tips regarding power consumption were deduced for the polyphase implementation form. The aim of this work is to help a system designer to select an efficient implementation for FIR in terms of power consumption without having to implement and synthesize the different possible solutions. The proposed method is applied for STMicroelectronics libraries 90 nm and 65 nm low power then validated with a use case of multistandard receiver designing.

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“…As a consequence, the general expression of the static power consumption for a direct form FIR filter (Figure 2) in the 90 nm technology could be written as shown in (9).…”

Section: Static Power Consumption Model Thementioning

confidence: 99%

Power Consumption Models for Decimation FIR Filters in Multistandard Receivers

et al. 2012

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“…The DCFS unit not only selects the channel but it also decreases the number of samples in a manner that a constant-sized accumulator can be used for each data rate, resulting in significant reduction of the complexity. One of the most known and efficient approaches to design a decimator filter is the use of a comb filter [11]. The Comb filters are multiplierless and can efficiently be implemented as shown in Fig.…”

Section: T (K) = N(k) H(k)+q(k) H(k)+i S (K) H(k)mentioning

confidence: 99%

Design and implementation of a multirate sub-sampling front-end in software radio systems

Yuce

Liu²

Proceedings. 2004 IEEE Radio and Wireless Conference (IEEE Cat. No.04TH8746)

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This paper analyzes the design of a multirate subsampling front-end for software radio systems. This front-end is well suited for software radios due to the limited dynamic range of ADC's in today's technology. It provides low power and high integration. The front-end also incorporates programmable digital decimation stages to accommodate variable bit rates. The impact of non-idealities in the ADC on the system performance requirement is also adressed.

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“…However most of the reported decimation filter designs have focused only on the integral decimation between Σ∆ ADC sampling rate and the Nyquist rate. These filters usually assume that any subsequent fractional sample rate conversion between the Nyquist rate and the symbol rate can be performed efficiently by a resampler operating in a low OSR environment after the integral decimation chain [78,80,81,83]. While the interferers and blockers attenuation requirements progressively decrease down the decimation chain, a fractional SRC stage operating in a high OSR environment needs to attenuate potential aliasing components only within a very narrow band.…”

Section: Implementation Of the Dfe In Existing Sdr Baseband Architectmentioning

confidence: 99%

“…The practical problem of supplying multiple clock signals has not been studied in most of the existing multistandard multistage decimation filter designs [62,78,80,81] for each standard from a single reference signal [148]. Unlike traditional integer-N PLLs, which have only an integer frequency divider in the PLL feedback loop, the fractional-N PLL frequency divider can assume rational values.…”

Section: Clockingmentioning

confidence: 99%

“…These stages cannot be readily reused because of standard dependent bandedges and stopband attenuation parameters.The few works that have touched upon the issue of filter stage reusability have limited their scope to a very small set of standards, hence the results are not easily extendible to a multistandard radio, that is capable of supporting arbitrary number of standards having arbitrary specifications. Most of the reported decimation filter designs which handle only integral decimation loads, partition the above load between a CIC stage, a halfband stage and FIR stage[78,80,81,83,84], where the halfband and last stage FIR filter decimate by a factor of 2. In[85] the authors propose a cascade of a CIC stage, two halfband stages and a FIR stage for the DFE.…”

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confidence: 99%

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Design of a low-power, reconfigurable digital front-end for a multimode SDR handset

Michael.¹

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Research often feels like a lonesome enterprise. But there are many, who consciously and subconsciously play the roles of enablers and catalysts. I would like to take this opportunity to thank them all. My supervisor, Assoc. Prof. Vinod A Prasad, whose soft, firm and reassuring hand has been the guiding force in my research work. Prof. Christophe Moy, for his constant support and guidance, and for making my stints at Supelec, Rennes, so enjoyable. Prof. Jacques Palicot, whose sharp observations played a critical role in shaping this thesis. Nanyang Technological University, for supporting me with the Graduate Research Scholarship, which allowed me to not worry about finances and just focus on the research. The French Embassy of Singapore, for supporting me with the Merlion PhD grant and for facilitating the research collaboration with the SCEE team at Supelec, Rennes. Dr. Mahesh Panicker, for helping me take the first baby steps in research. My friends, Thilaga, Ram, and Prashob for taking my mind off work, and for making me look forward to each day in the lab. I will miss the innumerable discussions we had. Dr. Smitha Sreekumar, a friend, guide and mentor, without whom the PhD experience wouldn't have been the same. And last, but not the least, my parents and my teachers, who shaped me into the person I am today.

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On design and implementation of a decimation filter for multistandard wireless transceivers

Cited by 28 publications

References 14 publications

Power Consumption Models for Decimation FIR Filters in Multistandard Receivers

Power Consumption Models for Decimation FIR Filters in Multistandard Receivers

Design and implementation of a multirate sub-sampling front-end in software radio systems

Design of a low-power, reconfigurable digital front-end for a multimode SDR handset

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