On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities

Communication concept for adaptive intelligent run-time systems supporting distributed reconfigurable embedded systems

“…In the following we want to give a short overview on our related previous work and the system concept. One of our previous successful approaches consisted in the development and implementation of a first run-time reconfigurable system-on-chip, supporting flexible ondemand hardware-task switching and a sophisticated runtime reconfiguration and task management mechanisms on Xilinx Virtex II FPGAs [9,18,19]. By exploiting the column-wise reconfiguration possibilities of Xilinx Virtex II FPGAs it offers at run-time a set of functionalities which are switched on demand during operation in a timemultiplexed way, so that a larger set of functionalities appears to be available to the user [18,19].…”

“…One of our previous successful approaches consisted in the development and implementation of a first run-time reconfigurable system-on-chip, supporting flexible ondemand hardware-task switching and a sophisticated runtime reconfiguration and task management mechanisms on Xilinx Virtex II FPGAs [9,18,19]. By exploiting the column-wise reconfiguration possibilities of Xilinx Virtex II FPGAs it offers at run-time a set of functionalities which are switched on demand during operation in a timemultiplexed way, so that a larger set of functionalities appears to be available to the user [18,19]. Furthermore the internal bus-system was modified, so that local bandwidth-and topology-adaptive Networks-on-Chip (NoC) [2] can be created at run-time, allowing optimized energy and resource saving communication and operation modes between the instantiated modules [9].…”

“…standard CPU, FPGA (soft-core CPU) or DSP) or on the same chip as well. The local sub-controllers are responsible for the management of local run-time reconfiguration and other sub-tasks like local task/ resource management and communication issues [18,19]. It should be noted that the system as shown in figure 1 can be comprehended as distributed system built of discrete devices.…”

“…Nevertheless the proposed concept can be realized as system-on-chip as well. Since we have already described detailed aspects of the proposed system's resource-allocation-management strategies and CBR-approach in earlier papers [18,19,20] we will focus in this contribution on another important aspect, the system's communications architecture providing transparent communication between applications and their allocated low-level sub-systems.…”

“…Reconfigurable computing systems have already shown the ability to greatly accelerate program execution, thereby providing a high-performance alternative to pure software-based implementations and a programmable alternative to expensive ASICs. The development of new architectural hardware/ software system concepts [3,10,13,19,24] by exploiting these powerful features of flexible and adaptive hardwareaccelerated coprocessors in combination with a design paradigm shift is an adequate approach to adapt to the market's requirements. Nevertheless the availability of the best superior reconfigurable architectures will not guarantee their success, if no sophisticated control and management mechanisms are provided by the system developers dealing with fault tolerance aspects and application scenarios with dynamically changing power/performance constraints.…”