On Deadlock Problem of On-Chip Buses Supporting Out-of-Order Transactions

Chang, Chin-Yao; Lee, Kuen-Jong

doi:10.1109/tvlsi.2013.2248765

Cited by 2 publications

(7 citation statements)

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“…With the above out-of-order mechanism, interconnect bandwidth and efficiency can be greatly improved; however, it may lead to the deadlock problem [3], [5], [9], which does not occur in traditional protocols supporting only in-order transactions. The conventional deadlock that occurs in traditional protocols is different from the ID deadlock that occurs in advanced bus protocols.…”

Section: Introductionmentioning

confidence: 99%

“…In the conventional deadlock, the relation between masters and slaves is similar to that between processes and resources in an operating system where a deadlock occurs when there exists a circular wait-and-hold relation among a set of processes and resources [11]. In advanced bus protocols, a deadlock occurs due to the out-of-order transactions that are tagged with IDs supported by these protocols [3].…”

Section: Introductionmentioning

confidence: 99%

“…Research work deadlock avoidance by least stalling (DALS) [3] builds complicated detection and prediction logics to check whether a deadlock scenario will occur. To guarantee the correctness, all necessary and sufficient conditions need to be encoded into the detection and prediction logics.…”

Section: Introductionmentioning

confidence: 99%

“…Unlike previous ID checking schemes [3], [9] which are implemented in the interconnect controller and assuming IDs are already assigned, in this brief, we propose a novel ID assignment scheme that assigns deadlock-free IDs to out-of-order transactions. We will show that our ID assignment can be implemented on masters with little hardware overhead but can significantly reduce the number of transaction stalls.…”

Section: Introductionmentioning

confidence: 99%

“…We perform benchmark simulations for ×264 [10] and fast Fourier transform (FFT) [4] to show the usefulness of the proposed ID assignment approach. Experimental results show that, on average, the proposed scheme has 83% stall cycle reduction compared with CDAS [9] and 77% stall cycle reduction compared with DALS [3]. If we allow dynamic adjustment of the SPG, on average, the proposed scheme has 87% stall cycle reduction compared with CDAS [9] and 82% stall cycle reduction compared with DALS [3].…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols

Chou

Chen

Yang

et al. 2016

IEEE Trans. VLSI Syst.

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In a modern system-on-chip design, hundreds of cores and intellectual properties can be integrated into a single chip. To be suitable for high-performance interconnects, designers increasingly adopt advanced interconnect protocols that support novel mechanisms of parallel accessing, including outstanding transactions and out-of-order completion of transactions. To implement those novel mechanisms, a master tags an ID to each transaction to decide in-order or out-of-order properties. However, these advanced protocols may lead to transaction deadlocks that do not occur in traditional protocols. To prevent the deadlock problem, current solutions stall suspicious transactions and in certain cases, many such stalls can incur serious performance penalty. In this brief, we propose a novel ID assignment mechanism that guarantees the issued transactions to be deadlock-free and results in significant reduction in the number of transaction stalls issued by masters. Our experimental results show encouraging performance improvements compared with previous works with little hardware and power overheads.Index Terms-Advanced interconnect protocol, deadlock, system on chip (SoC). 1063-8210

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%