On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures

Kang, Kunhyuk; Park, Sang Phill; Kim, Keejong; Roy, Kaushik

doi:10.1109/tvlsi.2008.2010399

Cited by 53 publications

(21 citation statements)

References 18 publications

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“…The classification of instructions is a valuable mechanism to alleviate the guardbanding and improving performance: (i) within a fixed corner, by acquiring the knowledge about which class of instructions is running, the processor can adapt the guard-banding accordingly, without any need for the intrusive variability sensor/observer; (ii) across every corner, processor can adjust its guard-banding for all class of instructions by using a lowoverhead variability observer, e.g. PLL [2], RO [13].…”

Section: B Variability Among Pipeline Stagesmentioning

confidence: 99%

“…Both static and dynamic variations arise from different physical sources such as: (i) static inherent process parameter variations, e.g. channel length and threshold voltage variations due to random dopant fluctuations and sub-wavelength lithography; (ii) dynamic environmental variations in ambient condition such as temperature fluctuations and supply voltage droops [2]. Static process variations can sometimes be mitigated through binning or by post-silicon tuning, while dynamic variations change as a function of time and environment, and therefore cannot be compensated by static pre-and post-silicon tuning.…”

Section: Introductionmentioning

confidence: 99%

“…In a similar vein, Razor [7] storage devices have been used in a 65nm ARM ISA processor [12], running at frequencies over 1GHz, where fast dynamic variations are significant. Less intrusive and low-overhead on-chip variability sensors using PLLs [2] and ring oscillators (RO) [13] have been proposed to detect process, supply voltage, and temperature variations.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Analysis of instruction-level vulnerability to dynamic voltage and temperature variations

Rahimi

Benini

Gupta

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-Variation in performance and power across manufactured parts and their operating conditions is an accepted reality in aggressive CMOS processes. This paper considers challenges and opportunities in identifying this variation and methods to combat it for improved computing systems. We introduce the notion of instruction-level vulnerability (ILV) to expose variation and its effects to the software stack for use in architectural/compiler optimizations. To compute ILV, we quantify the effect of voltage and temperature variations on the performance and power of a 32-bit, RISC, in-order processor in 65nm TSMC technology at the level of individual instructions. Results show 3.4ns (68FO4) delay variation and 26.7x power variation among instructions, and across extreme corners. Our analysis shows that ILV is not uniform across the instruction set. In fact, ILV data partitions instructions into three equivalence classes. Based on this classification, we show how a low-overhead robustness enhancement techniques can be used to enhance performance by a factor of 1.1x−5.5x.

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Section: B Variability Among Pipeline Stagesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Analysis of instruction-level vulnerability to dynamic voltage and temperature variations

Rahimi

Benini

Gupta

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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“…Generic monitors range from simple inverter-based ring oscillators (ROs) to more sophisticated process-specific ROs (PSROs) [2] and alternative monitoring structures such as phase-locked loops (PLLs) [11]. However, such generic monitors are inadequate to capture design characteristics such as mix of device types, which cause differing responses to process variations.…”

Section: Introductionmentioning

confidence: 99%

DDRO: A novel performance monitoring methodology based on design-dependent ring oscillators

Chan

Gupta²,

Kahng

et al. 2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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Abstract-As CMOS technology scales, circuit performance becomes more sensitive to manufacturing and environmental variations. Hence, there is a need to measure or monitor circuit performance during manufacturing and at runtime. Since each circuit may have different sensitivities to process variations, previous works have focused on synthesis of circuit performance monitors that are specific to a given design. In this work, we study the potential benefit of having multiple design-dependent monitors. We develop a systematic approach to the synthesis of multiple design-dependent monitors, as well as a corresponding delay estimation method.Our approach synthesizes design-dependent ring oscillators (DDROs) using standard library gates. This has the advantage of quick design turnaround time and reduced schedule impact, because the DDRO implementation can leverage automation in conventional implementation flows. Our delay estimation method seeks to minimize the number of parameters as well as computing resources (i.e., to limit information storage and exchange) used in delay estimation based on monitoring results. Experiments show that our delay estimation method using multiple DDROs reduces overestimation (timing margin) by up to 25% compared to use of a single DDRO.

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“…Such a delayed response arrival, after the triggering edge of the clock signal that drive the memory elements at the outputs of the combinational block, will produce an erroneous value and the generation of a timing error on the data stored in the pertinent memory element. A number of error detection techniques have been proposed in the open literature [8]- [14]. These sense the delayed circuit response and provide error tolerance using time redundancy approaches.…”

mentioning

confidence: 99%

Timing error tolerance in nanometer ICs

Valadimas

Tsiatouhas

Arapoyanni

2010

2010 IEEE 16th International on-Line Testing Symposium

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Abstract-Timing error tolerance turns to be an important design parameter in nanometer technology, high speed and high complexity integrated circuits. In this work, we present a low cost, multiple timing error detection and correction technique, which is based on a new Flip-Flop design. The proposed design approach provides timing error tolerance at the small penalty of one clock cycle delay in the circuit operation for each error correction. In addition, it is characterized by very low silicon area requirements compared to previous design schemes in the open literature. The proposed technique has been applied in a 90nm pipeline design of a digital FIR filter and the simulation results validated its efficiency.

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On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures

Cited by 53 publications

References 18 publications

Analysis of instruction-level vulnerability to dynamic voltage and temperature variations

Analysis of instruction-level vulnerability to dynamic voltage and temperature variations

DDRO: A novel performance monitoring methodology based on design-dependent ring oscillators

Timing error tolerance in nanometer ICs

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