DDRO: A novel performance monitoring methodology based on design-dependent ring oscillators

Abstract

Abstract-As CMOS technology scales, circuit performance becomes more sensitive to manufacturing and environmental variations. Hence, there is a need to measure or monitor circuit performance during manufacturing and at runtime. Since each circuit may have different sensitivities to process variations, previous works have focused on synthesis of circuit performance monitors that are specific to a given design. In this work, we study the potential benefit of having multiple design-dependent monitors. We develop a systematic approach to the synthesis of multiple design-dependent monitors, as well as a corresponding delay estimation method.Our approach synthesizes design-dependent ring oscillators (DDROs) using standard library gates. This has the advantage of quick design turnaround time and reduced schedule impact, because the DDRO implementation can leverage automation in conventional implementation flows. Our delay estimation method seeks to minimize the number of parameters as well as computing resources (i.e., to limit information storage and exchange) used in delay estimation based on monitoring results. Experiments show that our delay estimation method using multiple DDROs reduces overestimation (timing margin) by up to 25% compared to use of a single DDRO.

Underdesigned and Opportunistic Computing in Presence of Hardware Variability

“…Such structures are inserted (in a sparse manner) to capture hardware characteristics of interest. Several examples exist in the literature to monitor various circuit characteristics (e.g., achievable frequency [23], leakage power [24], or aging [25]). The challenge is to minimize the overheads introduced by the monitoring circuits; these overheads take the form of area, delay, and/or power, as well as design complexity while retaining accuracy.…”

ReSCALE: Recalibrating sensor circuits for aging and lifetime estimation under BTI

“…We can also use D U of M (tm i ) instead of Dwc(tm i ), which would require only two STA runs as explained in Sec. III-B, and reduce presilicon computation at the cost of accuracy 3 . The knowledge of the nearcritical paths of the CUT under the worst-case workload is also available from the presilicon analysis.…”

SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology

“…Methods as in [3] or [4] can also be applied to synthesize a replica-like path to reduce the margin for delay mismatch due to global variation.…”

“…Canary or replica circuits [2], [3] are stand-alone circuits which are intended to mimic the timing behavior of the original circuits. The delay of the real circuit can be estimated through measuring delay of the replicas.…”

“…The delay of the real circuit can be estimated through measuring delay of the replicas. Tunable [4] and design-dependent [3] replica circuits can reduce the mismatch of the real circuit and replica. Replica monitors are usually non-intrusive, but may fail to capture the variations that are local to real circuits such as random manufacturing variations and circuit aging.…”