On‐chip tunable Memristor‐based flash‐ADC converter for artificial intelligence applications

Humood, Khaled; Mohammad, Baker; Abunahla, Heba; Azzam, Anas

doi:10.1049/iet-cds.2019.0293

Cited by 13 publications

(3 citation statements)

References 55 publications

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“…Humood et al combined ReRAM devices with a conventional flash ADC scheme. In a flash ADC, resistors are used to generate fixed reference voltages to which the input is compared Humood et al (2019). Humood et al replaced the resistors with ReRAM devices, which can be programmed, resulting in a post-fabrication tunable ADC.…”

Section: Related Workmentioning

confidence: 99%

All-in-Memory Brain-Inspired Computing Using FeFET Synapses

et al. 2022

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The separation of computing units and memory in the computer architecture mandates energy-intensive data transfers creating the von Neumann bottleneck. This bottleneck is exposed at the application level by the steady growth of IoT and data-centric deep learning algorithms demanding extraordinary throughput. On the hardware level, analog Processing-in-Memory (PiM) schemes are used to build platforms that eliminate the compute-memory gap to overcome the von Neumann bottleneck. PiM can be efficiently implemented with ferroelectric transistors (FeFET), an emerging non-volatile memory technology. However, PiM and FeFET are heavily impacted by process variation, especially in sub 14 nm technology nodes, reducing the reliability and thus inducing errors. Brain-inspired Hyperdimensional Computing (HDC) is robust against such errors. Further, it is able to learn from very little data cutting energy-intensive transfers. Hence, HDC, in combination with PiM, tackles the von Neumann bottleneck at both levels. Nevertheless, the analog nature of PiM schemes necessitates the conversion of results to digital, which is often not considered. Yet, the conversion introduces large overheads and diminishes the PiM efficiency. In this paper, we propose an all-in-memory scheme performing computation and conversion at once, utilizing programmable FeFET synapses to build the comparator used for the conversion. Our experimental setup is first calibrated against Intel 14 nm FinFET technology for both transistor electrical characteristics and variability. Then, a physics-based model of ferroelectric is included to realize the Fe-FinFETs. Using this setup, we analyze the circuit’s susceptibility to process variation, derive a comprehensive error probability model, and inject it into the inference algorithm of HDC. The robustness of HDC against noise and errors is able to withstand the high error probabilities with a loss of merely 0.3% inference accuracy.

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Section: Related Workmentioning

confidence: 99%

All-in-Memory Brain-Inspired Computing Using FeFET Synapses

et al. 2022

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“…Memristor, the fourth fundamental circuit element, was postulated by Chua in 1971 [1] and was recently realized by HP labs in 2008 [2]. The key features of memristor device such as low power, small area and relatively high switching speeds [3][4][5] make it a competitive candidate to be deployed in many emerging applications including memory, neuromorphic, sensing, and radio frequency (RF) switches [6][7][8][9][10][11] (see figure 1). In addition to the advantages mentioned above for memristor, the intrinsic variability in memristor electrical characteristics from cycle to cycle and from device to device has been utilized for security applications [12].…”

Section: Introductionmentioning

confidence: 99%

SecureMem: efficient flexible Pt/GO/Cu memristor for true random number generation

Abunahla

Humood

Alazzam

et al. 2021

Flex. Print. Electron.

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This work reports on flexible cost-effective memristor device synthesis, using Pt/GO/Cu structure. The memristor is fabricated on flexible substrate and it preserves its switching ability at a bending angle of up to 60 • . Compared to the state of the art, in our fabrication method, the graphene oxide (GO) film is deposited directly to the device using spin coating. The fabricated memristor stack exhibits tunable volatility based on the used compliance current, which expands its application horizon for memory, computing and security schemes. In this work, the non-volatile regime along with the natural stochasticity of the switching behavior of the device, named SecureMem, are utilized for efficient true random number generation. A prototype of the full system interfacing with microcontroller is built to get SecureMem ready for integration with other circuits and systems. The randomness of the data generated by SecureMem prototype is confirmed by passing all National Institute of Standards and Technology tests without any post-processing or hardware overhead. SecureMem is considered a great asset as it provides new insights for highly efficient cost-effective hardware security in smart wearable devices.

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“…For example, a hybrid CMOS-memristor logic gate (known as memristor-ratioed logic (MRL)) has been deployed in the digital blocks of the pipeline ADC to decrease the clock delay further and increase the logic density [12,13]. A memristor-based flash ADC was also provided in [14]. In this work, a successive approximation register analog to digital converter (SAR-ADC) using the proposed memristor DAC has been provided to achieve low area and low power, as will be explained in Section 5.…”

Section: Introductionmentioning

confidence: 99%

Design of a Memristor-Based Digital to Analog Converter (DAC)

Fahmy

Zorkany

2021

Electronics

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A memristor element has been highlighted in recent years and has been applied to several applications. In this work, a memristor-based digital to analog converter (DAC) was proposed due to the fact that a memristor has low area, low power, and a low threshold voltage. The proposed memristor DAC depends on the basic DAC cell, consisting of two memristors connected in opposite directions. This basic DAC cell was used to build and simulate both a 4 bit and an 8 bit DAC. Moreover, a sneak path issue was illustrated and its solution was provided. The proposed design reduced the area by 40%. The 8 bit memristor DAC has been designed and used in a successive approximation register analog to digital converter (SAR-ADC) instead of in a capacitor DAC (which would require a large area and consume more switching power). The SAR-ADC with a memristor-based DAC achieves a signal to noise and distortion ratio (SNDR) of 49.3 dB and a spurious free dynamic range (SFDR) of 61 dB with a power supply of 1.2 V and a consumption of 21 µW. The figure of merit (FoM) of the proposed SAR-ADC is 87.9 fj/Conv.-step. The proposed designs were simulated with optimized parameters using a voltage threshold adaptive memristor (VTEAM) model.

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On‐chip tunable Memristor‐based flash‐ADC converter for artificial intelligence applications

Cited by 13 publications

References 55 publications

All-in-Memory Brain-Inspired Computing Using FeFET Synapses

All-in-Memory Brain-Inspired Computing Using FeFET Synapses

SecureMem: efficient flexible Pt/GO/Cu memristor for true random number generation

Design of a Memristor-Based Digital to Analog Converter (DAC)

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