On-chip SiGe transmission line measurements and model verification up to 110 GHz

On-chip CMOS coplanar transmission line measurements and model verification up to 50 GHz

“…The vertical separation between the signal pad and the bottom shielding was only 1.6 micron, resulting in high capacitive and low inductive effects. In other Tline test sites [1], higher vertical separation to the bottom shielding was used (9.25 micron) which required the additional use of the short pad structure in the de-embedding process. It should be noted that the pad capacitance limits the valid measurement frequency range up to the frequency where the pad capacitance shunt impedance becomes comparable or smaller than the measured T-line characteristic impedances.…”

“…While microstrip T-lines [1] are used more in SiGe RF and millimeter wave designs, coplanar transmission lines [2] are used more in RF CMOS and high speed CMOS digital designs, where the high density Manhattan wire structure prevents from using the bottom metallic shield in most cases. Compact semi-analytical parametric models for these standard transmission line types have been developed as part of an interconnect-aware analog and mixed signal (AMS) design methodology [2,3] and integrated within the IBM CMOS design kits.…”

Analysis and characterization of microstrip structures up to 90 GHz in SiGe BiCMOS

“…As evident from [4] - [9] considerable effort has been made on characterization of on-chip transmission lines up to the 110 GHz regime. In [4] line model verification has been made by applying two different de-embedding techniques and results are compared with IE3D simulation models.…”

“…In [4] line model verification has been made by applying two different de-embedding techniques and results are compared with IE3D simulation models. Dependency of line parameters on factors like line dimensions and choice of the metal layer in the stack is studied in [6].…”

Extracting characteristic impedance in low-loss substrates

“…However, the accuracy of TRL depends on the reliable determination of the characteristic impedance (Z c ) of the TL that establishes the reference for the calibrated data [2]. For years, the extremely simple method in [3] has been used to obtain Z c in semiconductor [4] as well as in printed circuit board (PCB) technologies [5]. Unfortunately, this method neglects the effect of the per unit length conductance (G) of the TL by assuming that the leakage currents and the effective loss tangent (tand eff ) of the dielectric environment surrounding the line are very small.…”