On-Chip Power Delivery and Management

P.-Vaisband, Inna; Jakushokas, Renatas; Popovich, Mikhail; Mezhiba, Andrey V.; Köse, Selçuk; Friedman, Eby G.

doi:10.1007/978-3-319-29395-0

Cited by 75 publications

(18 citation statements)

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“…The supply and threshold voltage extent to decrease for maintaining highest performance and lowest power requirements. Total power (Ptot), dynamic power (Pdynamic), and static power (Pstatic) dissipation in a CMOS circuit is given by [13,14]…”

Section: Dynamic Voltage Scaling (Dvs) and Body Bias Voltage Scaling mentioning

confidence: 99%

Multi-objective Pareto front and particle swarm optimization algorithms for power dissipation reduction in microprocessors

Sulaiman¹

2020

IJECE

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The progress of microelectronics making possible higher integration densities, and a considerable development of on-board systems are currently undergoing, this growth comes up against a limiting factor of power dissipation. Higher power dissipation will cause an immediate spread of generated heat which causes thermal problems. Consequently, the system's total consumed energy will increase as the system temperature increase. High temperatures in microprocessors and large thermal energy of computer systems produce huge problems of system confidence, performance, and cooling expenses. Power consumed by processors are mainly due to the increase in number of cores and the clock frequency, which is dissipated in the form of heat and causes thermal challenges for chip designers. As the microprocessor’s performance has increased remarkably in Nano-meter technology, power dissipation is becoming non-negligible. To solve this problem, this article addresses power dissipation reduction issues for high performance processors using multi-objective Pareto front (PF), and particle swarm optimization (PSO) algorithms to achieve power dissipation as a prior computation that reduces the real delay of a target microprocessor unit. Simulation is verified the conceptual fundamentals and optimization of joint body and supply voltages (Vth-VDD) which showing satisfactory findings.

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Section: Dynamic Voltage Scaling (Dvs) and Body Bias Voltage Scaling mentioning

confidence: 99%

Multi-objective Pareto front and particle swarm optimization algorithms for power dissipation reduction in microprocessors

Sulaiman¹

2020

IJECE

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“…• Power conversion, regulation, and management -each UD contains power conversion and regulation circuits, for example a buck converter and linear drop out (LDO) regulators. In addition to conversion and regulation, UDs support power management across the entire Si-IF [9]. • Synchronization -NoIF supports clock management through circuits for multi-clock domains within the UDs.…”

Section: Overview Of Network On Interconnect Fabricmentioning

confidence: 99%

“…Existing NoC power management concepts [9] are adopted for the NoIF. Each node communicates unique power requirements to other nodes and the NoIF dynamically adapts the power conversion and delivery schemes to ensure high quality of power for each device, stability of the power system [13], and security.…”

Section: Power Conversion and Managementmentioning

confidence: 99%

Network on interconnect fabric

Vaisband¹,

Bajwa²,

Iyer³

2018

2018 19th International Symposium on Quality Electronic Design (ISQED)

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Silicon interconnect fabric (Si-IF) supports integration of bare dies using thermal compression bonding on a Si wafer substrate. Fine pitch (2 to 10 µm) horizontal and vertical interconnects are feasible within the Si-IF using standard Si processing techniques. A network on interconnect fabric (NoIF) is proposed in this paper. The NoIF enables integration of ultra large scale heterogeneous systems within the technologically mature Si-IF platform. NoIF is based on utility dies which serve as intelligent nodes within the network. NoIF enables global communication, power conversion and management, synchronization, processing and memory capabilities, redundancy allocation, and test of the Si-IF, and the utility and functional dies.

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“…Pseudocode of the Matlab algorithm is summarized in Algorithm 1. A typical LDO model [7] is used to describe a small signal response of the on-chip power supplies, and evaluate the output impedance of the power supplies and overall power delivery system.…”

Section: Circuit Performance Modelingmentioning

confidence: 99%

Automated Design of Stable Power Delivery Systems for Heterogeneous IoT Systems

Partin-Vaisband

2017

Proceedings of the Great Lakes Symposium on VLSI 2017

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Efficiently and reliably managing high quality power is a primary challenge in Internet of Things (IoT) systems. Based on current projections, future IoT will provide vast interconnectedness of embedded devices and sensors, many of which will be powered up wirelessly from spatially distributed power supplies or locally from energy harvesting sources. The energy budget, constrained by inherently lower quality of power of these non-traditional power sources, will become a critical system resource and a primary limiting factor for scalability of future IoT systems. Distributed on-chip power regulation is necessary for efficiently delivering high quality power to high performance heterogeneous integrated circuits (ICs). A multi-feedback system with distributed on-chip power supplies delivering current to billions of non-linear circuits is characterized by complex interactions among the heterogeneous power supplies and loads. These modern multifeedback systems exhibit high design complexity and degraded stability. No straightforward method exists to efficiently design a stable multi-feedback power delivery system. An automated design and analysis flow for stable, high quality power delivery is proposed in this work based on the passivity of heterogeneous integrated systems. The algorithm is evaluated based on ISPD benchmark circuits and shows that the generated power delivery system addresses both the quality of power (QoP) and stability requirements. A distributed power delivery system is designed based on the passivity criterion and fabricated in 28 nm CMOS technology. The system is tested under a wide range of load, voltage, and temperature variations that are typical for modern heterogeneous ICs. The system exhibits high performance and stable response.

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On-Chip Power Delivery and Management

Cited by 75 publications

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Multi-objective Pareto front and particle swarm optimization algorithms for power dissipation reduction in microprocessors

Multi-objective Pareto front and particle swarm optimization algorithms for power dissipation reduction in microprocessors

Network on interconnect fabric

Automated Design of Stable Power Delivery Systems for Heterogeneous IoT Systems

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