On-chip lightweight implementation of reduced NIST randomness test suite

Suresh, Vikram; Antonioli, Daniele; Burleson, Wayne

doi:10.1109/hst.2013.6581572

Cited by 20 publications

(15 citation statements)

References 24 publications

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“…Many embedded tests implementations have been put forward in recent years for both FPGAs [3], [4], [5] and ASIC [3], [6]. However, all presented tests are tailored for independent, identically distributed (IID) number generators.…”

Section: Introductionmentioning

confidence: 99%

On-the-fly tests for non-ideal true random number generators

Yang

Rožić

Mentens

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-Hardware implementations of statistical tests are needed to detect failures and statistical weaknesses of entropy sources in True Random Number Generators on the fly. Current implementations of these tests work under the assumption that the entropy source produces independent, identically distributed (IID) numbers. However, some entropy sources produce non-IID data and rely on compression to provide the full entropy. Currently there are no embedded test implementations suitable for this type of entropy source. We provide the first FPGA implementation of embedded tests that estimate the generated min-Entropy and verify if it is within the expected boundaries.

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Section: Introductionmentioning

confidence: 99%

On-the-fly tests for non-ideal true random number generators

Yang

Rožić

Mentens

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Such an elaborate test and validation technique with huge test time and cost is not viable for low cost applications like RFID and smart cards. An alternate to post-Si testing could be using on-chip statistical tests in the form of a Built-In Self Test [14]. Further, the outcome of TRNG test/validation has to be utilized to perform appropriate post-processing or for circuit calibration.…”

Section: Background and Motivationmentioning

confidence: 99%

“…One of the popular test suites used for validating RNG circuits is the NIST statistical tests. A subset of these tests was optimized for hardware implementation in [14]. The BIST circuit or on-chip statistical tests can be used to estimate the bias in TRNG and perform additional postprocessing or circuit calibration.…”

Section: Testing Bias In True Random Number Generatorsmentioning

confidence: 99%

Post-Silicon Validation and Calibration of Hardware Security Primitives

Suresh

Kumar

et al. 2014

2014 IEEE Computer Society Annual Symposium on VLSI

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Physical Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) are gaining significant importance in the field of hardware security. These cryptographic primitives harness randomness from IC fabrication process and on-chip noise respectively; necessitating unconventional post-Silicon (Si) validation techniques. In this work, we present a brief survey of post-Si validation techniques for PUFs and TRNGs, highlighting the importance of testing PUFs resilience against novel attacks and monitoring bias in TRNGs. We also propose novel techniques for monitoring PUFs reliability and measuring bias in TRNGs. The proposed techniques do not only facilitate on-chip calibration for hardware security systems, but can also be used as a countermeasure against fault-attacks.

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“…However, the architecture of this design was not suitable for on-the-fly testing. Partially reconfigurable ASIC implementations of 6 NIST tests are presented in [12]. FPGA implementations of 8 different tests from the NIST test suite are presented in [13].…”

Section: A Previous Workmentioning

confidence: 99%

“…We use a simple approach of computing the inverse functions of the critical value and storing the precomputed constants, thereby skipping the most computationally intensive step. This approach is also used in [9], [13], [12].…”

Section: Sw Implementationsmentioning

confidence: 99%

Embedded HW/SW Platform for On-the-Fly Testing of True Random Number Generators

Yang¹,

Rožić²,

Mentens³

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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Abstract-We present a HW/SW platform for on-the-fly detection of failures and weaknesses in entropy sources. By splitting the operations between hardware and software, we achieve sufficient flexibility to control the level of significance of the tests. This approach also enables sharing resources between different tests thereby reducing the area and power. Statistical tests were selected from the NIST test suite. We propose several versions of hardware co-processors for monitoring random bit sequences, ranging from 52 slices (5 tests) to 552 slices (9 tests) on Spartan-6 FPGA. We are the first to provide implementations of the Serial test and the Approximate entropy test for on-the-fly monitoring.

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On-chip lightweight implementation of reduced NIST randomness test suite

Cited by 20 publications

References 24 publications

On-the-fly tests for non-ideal true random number generators

On-the-fly tests for non-ideal true random number generators

Post-Silicon Validation and Calibration of Hardware Security Primitives

Embedded HW/SW Platform for On-the-Fly Testing of True Random Number Generators

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