Post-Silicon Validation and Calibration of Hardware Security Primitives

Abstract

Physical Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) are gaining significant importance in the field of hardware security. These cryptographic primitives harness randomness from IC fabrication process and on-chip noise respectively; necessitating unconventional post-Silicon (Si) validation techniques. In this work, we present a brief survey of post-Si validation techniques for PUFs and TRNGs, highlighting the importance of testing PUFs resilience against novel attacks and monitoring bias in TRNGs. We also propose novel techniques for monitoring PUFs reliability and measuring bias in TRNGs. The proposed techniques do not only facilitate on-chip calibration for hardware security systems, but can also be used as a countermeasure against fault-attacks.