On-chip digital power supply control for system-on-chip applications

Meijer, Maurice; Gyvez, José Pineda de; Otten, Ralph H. J. M.

doi:10.1145/1077603.1077677

Cited by 20 publications

(12 citation statements)

References 8 publications

(5 reference statements)

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“…Work in [23]- [26] demonstrate techniques where this is no longer the case. Taking the work in [25], [26] as an example, they demonstrate a fine grained DVFS technique with switching times in nano seconds.…”

Section: Introductionmentioning

confidence: 99%

Power Minimisation for Real-Time Dataflow Applications

Nelson

Moreira

Molnos

et al. 2011

2011 14th Euromicro Conference on Digital System Design

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Abstract-Energy efficient execution of applications is important for many reasons, e.g. time between battery charges, device temperature. Voltage and Frequency Scaling (VFS) enables applications to be run at lower frequencies on hardware resources thereby consuming less power. Real-time applications have deadlines that must be met otherwise their output is devalued. Dataflow modelling of real-time applications enables off-line verification of the application's temporal requirements. In this paper we describe a method to reduce the combined static and dynamic energy consumption using a Dynamic VFS (DVFS) technique for dataflow modelled real-time applications that may be mapped onto multiple hardware resources. We achieve this by using an application's static slack in order to perform DVFS while still satisfying the application's temporal requirements. We show that by formulating a dataflow modelled application and its mapping as a convex optimisation problem, with energy consumption as the objective function, the problem can be solved with a generic convex optimisation solver, producing an energyoptimal constant frequency per application task. Our method allows task frequencies to be constrained such that, e.g. one frequency per application or per processor may be achieved.

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Section: Introductionmentioning

confidence: 99%

Power Minimisation for Real-Time Dataflow Applications

Nelson

Moreira

Molnos

et al. 2011

2011 14th Euromicro Conference on Digital System Design

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“…The integration of a DC-DC converter is especially useful when local supply generation is needed, for example in voltage-scaling techniques for digital ICs [1]. The IC is then divided into independent voltage islands, each of which is powered by an individual power supply with an output voltage that minimizes power consumption of the supplied voltage island.…”

Section: Introductionmentioning

confidence: 99%

A 65-nm-CMOS 100-MHz 87%-efficient DC-DC down converter based on dual-die system-in-package integration

Bergveld

Nowak

Karadi

et al. 2009

2009 IEEE Energy Conversion Congress and Exposition

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Document VersionPublisher's PDF, also known as Version of Record (includes final page, issue and volume numbers)Please check the document version of this publication:• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication Citation for published version (APA):Bergveld, H. J., Nowak, K., Karadi, R., Iochem, S., Ferreira, J., Ledain, S., ... Pommier, M. (2009). A 65-nm-CMOS 100-MHz 87%-efficient DC-DC down converter based on dual-die system-in-package integration. In Proc. IEEE Energy Conversion Congress and Exposition (ECCE'09), San Jose, USA, 20-24 Sept. 2009 (pp. 3698-3705 General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. Abstract --The increasing number of efficient voltage conversions realized in small volumes in many applications has introduced a trend towards small-form-factor DC-DC converters with integrated passives. Preferably, the DC-DC converter is integrated with the load, often in nm-CMOS, allowing for local supply optimization yielding increased power efficiency. However, energy-storage densities in nm-CMOS are low and silicon area is expensive. Therefore, to limit cost of monolithically integrated systems, passive components have low values, leading to very high switching frequencies, which compromises efficiency. This paper follows an alternative approach, where the active converter part is realized in 65-nm CMOS and the passive part in a low-cost high-density passiveintegration process. With the active die flip-chipped on the passive die a small System-in-Package (SiP) is obtained with a peak efficiency of 87.5% at 100 MHz switching frequency and 85 mW output power. This performance is mainly caused by the high quality of the integrated passives.

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“…By reducing the supply voltage and clock frequency, considerable power can be saved while and are generally fixed for a specific application. Over the years, researchers have proposed different hardware adaptive power management infrastructures to construct low power system-on-chip (SoC) integrated circuits [1][2][3][4][5][6]. Clock-gating, dynamic voltage scaling (DVS), dynamic frequency scaling (DFS), dynamic voltage and frequency scaling (DVFS) and power gating are some examples of the proposed approaches that today's SoCs use [1][2][3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

“…Over the years, researchers have proposed different hardware adaptive power management infrastructures to construct low power system-on-chip (SoC) integrated circuits [1][2][3][4][5][6]. Clock-gating, dynamic voltage scaling (DVS), dynamic frequency scaling (DFS), dynamic voltage and frequency scaling (DVFS) and power gating are some examples of the proposed approaches that today's SoCs use [1][2][3][4][5][6]. To dynamically adjust the supply voltage, we require three components: a circuit that can operate over a wide supply voltage range, a power manager that can intelligently vary the frequency of operation, and a power supply controller to set a minimum supply voltage for the desired operating frequency.…”

Section: Introductionmentioning

confidence: 99%

Dynamic voltage scaling based on supply current tracking using fuzzy Logic controller

Pourshaghaghi

Gyvez

2009

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

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Abstract-It has been demonstrated that dynamic voltage and frequency scaling (DVFS) leads to a considerable saving in dynamic and static power of a processor. In this paper, we present an adaptive framework that can be used to dynamically adjust supply voltage and frequency of a processor under different application workloads. Voltage scaling decisions are made by a fuzzy Logic (FL) block based on variations of the processor's workload. By observing the supply-current of the processor and also its variation rate, the FL block can drive the processor to operate at the lowest possible voltage and also the corresponding minimum frequency, in which a specific application can meet all of its deadlines under time-constrained operation. As the voltage can change at the same time as the workload varies, significant savings in both dynamic and static power are achieved. Simulation results show that our approach outperforms a PID controller under distinct working loads.

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On-chip digital power supply control for system-on-chip applications

Cited by 20 publications

References 8 publications

Power Minimisation for Real-Time Dataflow Applications

Power Minimisation for Real-Time Dataflow Applications

A 65-nm-CMOS 100-MHz 87%-efficient DC-DC down converter based on dual-die system-in-package integration

Dynamic voltage scaling based on supply current tracking using fuzzy Logic controller

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