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We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micron (DSM) integrated circuit design. Our layout "fabric" scheme eliminates the conventional notion of power and ground routing on the integrated circuit die. Instead, power and ground are essentially "pre-routed" all over the die. By a clever arrangement of power/ground and signal pins, we almost completely eliminate the capacitive effects between signal wires. Additionally, we get a power and ground distribution network with a very low resistance at any point on the die. Another advantage of our scheme is that the arrangement of conductors ensures that onchip inductances are uniformly negligible. Finally, characterization of the circuit delays, capacitances and resistances becomes extremely simple in our scheme, and needs to be done only once for a design.We show how the uniform parasitics of our fabric give rise to a reliable and predictable design. We have implemented our scheme using public domain layout software. Preliminary results show that it holds much promise as the layout methodology of choice in DSM integrated circuit design.

In this paper a shift is proposed in the design of vlsi circuits. In conventional design higher levels of synthesis have t o d eliver a gate and net list, from which l a yout synthesis has to build a mask speci cation for manufacturing. Analysis, mainly timing analysis, is built in a feedback loop to catch violations of timing requirements before sign-o . These violations are used to hand an updated speci cation to synthesis. Such iteration is not desirable, and for really high performance not feasible. To come to a design ow, higher level synthesis should distribute delay o ver the functional elements and interconnect, and layout synthesis should use its degrees of freedom to realize those delays.