On-chip detection methodology for break-even time of power gated function units

Usami,; Matsunaga,; Koyama,; Ikebuchi,; Amano,; Nakamura,

doi:10.1109/islped.2011.5993643

Cited by 18 publications

(11 citation statements)

References 7 publications

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“…Low-power techniques such as clock gating [31], power gating [43] [21] or DVFS can be combined with vector micro-architectures to further reduce power consumption and increase energy efficiency. H. Inoue presented in [22] a paper studying the impact of SIMD processors in power and energy efficiency in sorting algorithms.…”

Section: Power In Vector Processorsmentioning

confidence: 99%

Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies

et al. 2019

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Moore's Law predicted that the number of transistors on a chip would double approximately every two years. However, this trend is arriving at an impasse. Optimizing the usage of the available transistors within the thermal dissipation capabilities of the packaging is a pending topic.Multi-core processors exploit coarse-grain parallelism to improve energy efficiency. Vectorization allows developers to exploit data-level parallelism, operating on several elements per instruction and thus, reducing the pressure to the fetch and decode pipeline stages.In this paper we perform an analysis of different resource optimization strategies for vector architectures. In particular we expose the need to break down voltage and frequency domains for LLC, ALUs and vector ALUs if we aim to optimize the energy efficiency and performance of our system. We also show the need for a dynamic reconfiguration strategy that adapts vector register length at runtime.

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Section: Power In Vector Processorsmentioning

confidence: 99%

Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies

et al. 2019

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“…Therefore, the application requiring the use of the RA 3 can easily make use of the current application parameters to assess the required performance and determine the necessary resources to achieve it. Furthermore, as the reconfiguration is performed at the grain of applications, it is significantly above the observed breakeven time (BET) for power-gating techniques [Usami et al 2011]. The BET is the minimum time a component should be switched off so that the costs of powering it on and off are compensated and actual gains are observed.…”

Section: Resilient Adaptive Algebraic Architecturementioning

confidence: 99%

Adaptive Parallelism Exploitation under Physical and Real-Time Constraints for Resilient Systems

Itturiet

Nazar

Ferreira

et al. 2014

ACM Trans. Reconfigurable Technol. Syst.

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FÁBIO ITTURIET, GABRIEL NAZAR, RONALDO FERREIRA,ÁLVARO MOREIRA, and LUIGI CARRO, Universidade Federal do Rio Grande do Sul This article introduces the resilient adaptive algebraic architecture that aims at adapting parallelism exploitation of a matrix multiplication algorithm in a time-deterministic fashion to reduce power consumption while meeting real-time deadlines present in most DSP-like applications. The proposed architecture provides low-overhead error correction capabilities relying on the hardware implementation of the algorithm-based fault-tolerance method that is executed concurrently with matrix multiplication, providing efficient occupation of memory and power resources. The Resilient Adaptive Algebraic Architecture (RA 3 ) is evaluated using three real-time industrial case studies from the telecom and multimedia application domains to present the design space exploration and the adaptation possibilities the architecture offers to hardware designers. RA 3 is compared in its performance and energy efficiency with standard high-performance architectures, namely a GPU and an out-of-order general-purpose processor. Finally, we present the results of fault injection campaigns in order to measure the architecture resilience to soft errors.

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“…Its core has a fine-grained power gating mechanism which controls the power supply of functional units according to the fetched instruction [6]. Leak monitors [7] are provided to measure the leakage current. Two set associative instruction and data cache modules, the unified TLB and CP0 for supporting Linux operating system are also provided.…”

Section: Ii-a Geyser-cube and Cma-cubementioning

confidence: 99%

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect

Koizumi

Amano

Matsutani

et al. 2012

2012 International Conference on Field-Programmable Technology

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Cube-2 is a prototype of building block scalable reconfigurable accelerator using an inductive coupling interconnect. It is consisting of a ultra low leakage embedded processor Geyser and coarse-grained reconfigurable accelerators CMA (Cool Mega Array). A Geyser chip and multiple CMA chips are stacked, and a powerful network is formed by using the inductive coupling interconnect. The performance can be enhanced by increasing the number of CMA chips. JPEG decoder is implemented with a cooperation of Geyser and CMAs, and low power execution by controlling the power supply voltage of CMAs is demonstrated.

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On-chip detection methodology for break-even time of power gated function units

Cited by 18 publications

References 7 publications

Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies

Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies

Adaptive Parallelism Exploitation under Physical and Real-Time Constraints for Resilient Systems

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect

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