On-Chip Antenna Integration for Millimeter-Wave Single-Chip FMCW Radar, Providing High Efficiency and Isolation

Performance-Issues-Mitigation-Techniques for On-Chip-Antennas – Recent Developments in RF, MM-Wave, and Thz Bands With Future Directions

“…Gain of -3.8 dBi for monopole and -6.1 dBi for IFA has been obtained. (b) The use of PCB based cavity and special structures on the package of the chip: In [110], the authors have proposed solution of the challenges such as ohmic loss introduced by the silicon substrate, higher order substrate modes, and surface waves to the realization of 3 AoCs integrated in 60 GHz FMWC radar chip using Qubic4X SiGe BiCMOS process. After a detailed study and analysis, the authors have selected cavity-backed on-chip monopole antenna as antenna configuration because of its miniaturization and ability to solve the above-mentioned issues related to AoCs.…”

Determining the input reflection coefficient of integrated antennas using over-the-air measurements under near-field conditions

“…In first instance, a patch antenna has been used as AUT. Mainly because of its planar low-profile structure, this type of antenna is widely used in integrated antenna studies (see for instance [2][3][4][5][6][7][8]) and, therefore, a straightforward choice as a starting point for this assessment. In Fig.…”

“…To observe whether the obtained results can also be acquired using antennas different from a patch, two other antenna structures have been assessed. For this assessment, a monopole and dipole antenna are selected since these structures are found in multiple studies on integrated antennas [6][7][8][9]. In Figs 3(e) and 3(f), a CST model of the used planar monopole and dipole antenna are shown, respectively.…”

“…These handlers typically are embedded in a system which can be used to test and verify the functionality of the IC [1]. One of the current trends in the IC development is the integration of antennas on-chip or in the package of the IC [2][3][4][5][6][7][8][9]. This poses challenges in the production testing process of the packaged IC, as the antenna functionality has to be included.…”

Enhancement of transmission characteristics for the antenna system printed on silicon wafer substrate by using FSS‐based coplanar parallel reflector

“…The crosstalk noise among traces and circuits has become an unavoidable bottleneck in signal integrity design [4][5][6][7]. To overcome the limitation of global trace interconnection and to solve signal integrity issues in ultralarge-scale integrated circuits (ULSICs), such as system-on-chip (SoC) or network-on-chip (NoC), the on-chip antenna-based wireless interconnection method has been developed [8][9][10][11][12][13][14][15][16]. While, in practice, the commercial complementary metal oxide semiconductor (CMOS) technology often adopts lossy and highpermittivity silicon substrate leading to poor radiation and transmission performance of on-chip antenna systems [12][13][14][15].…”