On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures

Pétrot, Frédéric; Greiner, Alain; Gomez, Pascal

doi:10.1109/dsd.2006.73

Cited by 29 publications

(21 citation statements)

References 13 publications

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“…In the first experiment we compare three instances of FFT, which is executed on one pro- cessor without cache coherence operations. The instances are WT+WT, which means both private and shared data write-through cacheable, WB+NC, which means private date write-back cacheable and shared data noncacheable (as proposed in [11]), and our proposal, WB+WT, where private data is write-back cacheable and shared data is writethrough cacheable. Figure 9(a) shows the execution time for the three instances, and Figure 9(b) shows the total number of memory accesses for the three instances.…”

Section: Methodsmentioning

confidence: 99%

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A tuneable software cache coherence protocol for heterogeneous MPSoCs

Ophelders

Bekooij

Corporaal

2009

Proceedings of the 7th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis

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In a multiprocessor system-on-chip (MPSoC) private caches introduce the cache coherence problem. Here, we target at heterogeneous MPSoCs with a network-on-chip (NoC). Existing hardware cache coherence protocols are less suitable for MPSoCs because many off-the-shelf processors used in MPSoCs do not support these protocols. Furthermore, these protocols typically rely on global visibility and serialization of writes which does not match well with the parallel pointto-point communication provided by a NoC. Therefore, we propose a software cache coherence protocol, which can be applied in a heterogeneous MPSoC with a NoC. The software cache coherence protocol relies on explicit synchronization in the software. More specifically, caches are guaranteed to be coherent according to the Release Consistency model, on top of which we have implemented the standard Pthreads communication library. Heterogeneous MPSoCs with off-the-shelf processors can easily be supported, because processors are only required to provide cache control operations, e.g., clean and invalidate. All cache coherence operations are interruptible and do not impact the execution of tasks on other processors, therefore this protocol is suitable for predictable MPSoCs. Our software cache coherence protocol is implemented on an ARM926EJ-S MPSoC which is mapped on an FPGA. From experiments we conclude that the protocol overhead is low for the applications taken from the SPLASH-2 benchmark set. For these applications we observed a speedup between 1.89 and 2.01 on the two processor MPSoC.

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Section: Methodsmentioning

confidence: 99%

“…Cache coherence issues for NoC based MPSoCs are discussed in [11]. They propose to provide separate address ranges for shared and for private data.…”

Section: Related Workmentioning

confidence: 99%

A tuneable software cache coherence protocol for heterogeneous MPSoCs

Ophelders

Bekooij

Corporaal

2009

Proceedings of the 7th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis

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“…combine streaming and memory-mapped communication, and also do not show how to implement a specific memory-consistency model. The issue of memory consistency and ordering is addressed in [30] by only allowing one outstanding transaction. This, however, is overly restrictive and severely impairs the interconnect performance.…”

Section: Related Workmentioning

confidence: 99%

“…2) The use of distributed memories places requirements on the interconnect that must support an established memory consistency model [30], e.g. release consistency [10], to allow the programmer to reason about the order of memory operations.…”

Section: Introductionmentioning

confidence: 99%

An on-chip interconnect and protocol stack for multiple communication paradigms and programming models

Hansson

Goossens

2009

Proceedings of the 7th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis

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A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The diverse requirements, coupled with the IPs being developed by unrelated design teams, lead to multiple communication paradigms, programming models, and interface protocols that the on-chip interconnect must accommodate.Traditionally, on-chip buses offer distributed shared memory communication with established memory-consistency models, but are tightly coupled to a specific interface protocol. On-chip networks, on the other hand, offer layering and interface abstraction, but are centred around point-topoint streaming communication, and do not address issues at the higher layers in the protocol stack, such as memoryconsistency models and message-dependent deadlock.In this work we introduce an on-chip interconnect and protocol stack that combines streaming and distributed shared memory communication. The proposed interconnect offers an established memory-consistency model and does not restrict any higher-level protocol dependencies. We present the protocol stack and the architectural blocks and quantify the cost, both on the block level and for a complete SoC. For a multi-processor multi-application SoC with multiple communication paradigms and programming models, our proposed interconnect occupies only 4% of the chip area.

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“…Although software cache coherency is more complex to use, it outperforms hardware in terms of performance and energy usage [5]. Additionally, domain-specific architectures typically omit coherency at all [17], or leave the shared memory uncached [91].…”

Section: Weak-memory Hierarchymentioning

confidence: 99%

Programming models for many-core architectures: a co-design approach

Rutgers¹

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It is unlikely that general-purpose single-core performance will improve much in the coming years. The clock speed is limited by physical constraints, and recent architectural improvements are not as beneficial for performance as those were several years ago. However, the transistor count and density per chip still increase, as feature sizes reduce, and material and processing techniques improve. Given a limited single-core performance, but plenty of transistors, the logical next step is towards many-core.A many-core processor contains at least tens of cores and usually distributed memory, which are connected (but physically separated) by an interconnect that has a communication latency of multiple clock cycles. In contrast to a multicore system, which only has a few tightly coupled cores sharing a single bus and memory, several complex problems arise. Notably, many cores require many parallel tasks to fully utilize the cores, and communication happens in a distributed and decentralized way. Therefore, programming such a processor requires the application to exhibit concurrency. Moreover, a concurrent application has to deal with memory state changes with an observable (non-deterministic) intermediate state, whereas singlecore applications observe all state changes to happen atomically. The complexity introduced by these problems makes programming a many-core system with a single-core-based programming approach notoriously hard.The central concept of this thesis is that abstractions, which are related to (manycore) programming, are structured in a single platform model. A platform is a layered view of the hardware, a memory model, a concurrency model, a model of computation, and compile-time and run-time tooling. Then, a programming model is a specific view on this platform, which is used by a programmer.In this view, some details can be hidden from the programmer's perspective, some details cannot. For example, an operating system presents an infinite number of parallel virtual execution units to the application-details regarding scheduling and context switching of processes on one core are hidden from the programmer. On the other hand, a programmer usually has to take full control over separation, distribution, and balancing of workload among different worker threads. To what extent a programmer can rely on automated control over low-level platform-specific details is part of the programming model. This thesis presents modifications to different abstraction layers of a many-core architecture, in order to make the system as a whole more efficient, and to reduce the complexity that is exposed to the programmer via the programming model. viFor evaluation of many-core hardware and corresponding (concurrent) programming techniques, a 32-core MicroBlaze system, named Starburst, is designed and implemented on FPGA. On the hardware architecture level, a network-on-chip is presented that is tailored towards a typical many-core application communication pattern. All cores can access a shared memory, but as this ...

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On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures

Cited by 29 publications

References 13 publications

A tuneable software cache coherence protocol for heterogeneous MPSoCs

A tuneable software cache coherence protocol for heterogeneous MPSoCs

An on-chip interconnect and protocol stack for multiple communication paradigms and programming models

Programming models for many-core architectures: a co-design approach

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