On applying non-classical defect models to automated diagnosis

Saxena, J.; Butler, K.M.; Balachandran, H.; Lavo, D.B.; Chess, B.; Larrabee, T.; Ferguson, F.J.

doi:10.1109/test.1998.743256

Cited by 23 publications

(4 citation statements)

References 30 publications

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“…9 However, diagnosis studies on real devices with actual bridging defects created with focused ion beam equipment indicate that wired AND/OR behavior is also a relatively common occurrence. 10 In our study, surrogates were modeled as wired AND/OR bridges. The wired AND bridge models a short where a zero on either net dominates a logic one on the other net.…”

Section: Commercial Ic Surrogate Simulationmentioning

confidence: 99%

Defect-oriented testing and defective-part-level prediction

Dworak¹,

Wicker²,

Lee

et al. 2001

IEEE Des. Test. Comput.

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Section: Commercial Ic Surrogate Simulationmentioning

confidence: 99%

Defect-oriented testing and defective-part-level prediction

Dworak¹,

Wicker²,

Lee

et al. 2001

IEEE Des. Test. Comput.

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“…Fault diagnosis techniques [3][4][5][6][7][8][9][10][11][12][13][14] mainly differ from the type of defects/faults they target (e.g., delay, leakage, bridging faults), the fault models they are based on (e.g., stuck-at-fault, pseudostuck-at-fault, bridging fault, non classical models), and the information they use (e.g., logical output values, IB DDQ B ). In this paper, we specifically focus on bridging faults or defects (modeled as bridge resistors), as they still are dominant yield loss contributors.…”

Section: Introductionmentioning

confidence: 99%

3DSDM: A 3 data-source diagnostic method

Hariri

Thibeault

Proceedings. 16th IEEE Symposium on Computer Arithmetic

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The goal of this paper is to present a diagnosis method for bridging faults combining three different data sources: IB DDQ B measurements, logical behavior and layout parasitic capacitances. The resulting hybrid method constitutes a significant improvement over an existing one based on IB DDQ B probabilistic signatures. Combining these data contributes to reduce the number of potential fault sites to consider in the diagnosis process, and therefore accelerate this process. Simulation results show that the number of potential bridging fault sites is reduced from 0.5N(N-1) to less than N, where N is the number of nodes in the circuit under test.

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“…Fault diagnosis procedures may consider a specific fault model, e.g., stuck-at faults [1], bridging faults [2]- [8], interconnect stuck-open faults [9], or delay faults [10]- [13]. The fact that a defect may behave differently than a modeled fault is accommodated by using matching algorithms to identify the fault most likely to explain the faulty circuit behavior [14], [15].…”

Section: Introductionmentioning

confidence: 99%

Fault Diagnosis and Fault Model Aliasing

Pomeranz

Venkataraman²,

Reddy

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

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During fault diagnosis the existence of equivalent faults, or faults that are not distinguished by the test set applied to the circuit, can create ambiguity as to the location of a defect. This happens if the circuit-under-test produces a response that matches the circuit response in the presence of two faults in different locations of the circuit. Equivalence between faults of dif f erent models, or a test set that does not distinguish two such faults, can increase the ambiguity as to the defect location as well as its type. We refer to this phenomenon as fault model aliasing. We study the extent to which fault model aliasing can be expected to occur under various test sets. We also describe a test generation procedure that can reduce it.

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On applying non-classical defect models to automated diagnosis

Cited by 23 publications

References 30 publications

Defect-oriented testing and defective-part-level prediction

Defect-oriented testing and defective-part-level prediction

3DSDM: A 3 data-source diagnostic method

Fault Diagnosis and Fault Model Aliasing

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