Offset-Gate Structures for Increased Breakdown Voltages in Silicon-On-Insulator Transistors

Abstract

An offset-gate structure was used to fabricate p-channel MOS transistors in laser-recrystallized silicon-on-insulator (SOI) films.The breakdown voltage increased from about -18 V with a conventional gate structure to about -38 V with the offset gate and was then limited by bulk breakdown in the film, rather than by the high fields near the gate drain overlap region.Simulations indicate that breakdown voltages of about -60 V can be achieved in the structure used, provided that the back-surface fixed-charge density is limited to lX10" cm-2

3-D high-voltage CMOS ICs by recrystallized SOI merged with bulk control-unit

“…In addition to the ease of complete device isolation, SO1 has many inherent advantages such as simple fabrication process, small parasitic capacitance, latch-up free, high-speed, and highpacking density. In fact, several approaches have been made to realize high-voltage devices by utilizing SO1 structures such as SOS (11, SIMOX (2),and polysilicon TFT (3)as well as laser recrystallized SO1 (4,5).However, a conplete monolithic integration of SO1 high-power output circuits and low-voltage bulk CMOS control units has not been reported yet.…”